Dual Gate Oxide Amplifier Circuit Resolving Speed and Impact Ionization Trade-offs
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Solution Overview
Problem
Conventional amplifier circuits face limitations in achieving high speed operation, high DC gain, and wide dynamic range due to low frequency parasitic poles and impact ionization effects, which restrict their bandwidth and reliability.
Innovation Solution
A two-stage amplifier circuit fabricated using a dual gate oxide process with thick gate oxide high voltage MOS transistors and thin gate oxide low voltage MOS transistors, where only high speed low voltage transistors are used in the signal path, and the output common mode voltage is precisely controlled to minimize impact ionization and parasitic capacitance, thereby increasing the parasitic pole frequency and ensuring high speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low voltage MOS transistors are used in the signal path to achieve high speed operation, then bandwidth is improved, but impact ionization effects increase when output voltage reaches high values
Solution Approach 1:
The patent applies different transistor types in different locations of the circuit. Low voltage MOS transistors are used specifically in the signal path where high speed is critical, while high voltage MOS transistors are used in cascode configurations where voltage handling is critical. This spatial differentiation of transistor characteristics resolves the contradiction between speed and impact ionization resistance.
Solution Approach 2:
The patent uses a composite transistor architecture combining low voltage and high voltage MOS transistors in a dual-gate oxide process. The low voltage transistors provide high speed operation while the high voltage transistors provide immunity to impact ionization, creating a composite device system that achieves both high bandwidth and high reliability.
2Reliability
If high voltage MOS transistors are used to reduce impact ionization effects, then reliability is improved, but operating speed decreases
Solution Approach 1:
High voltage MOS transistors are strategically placed only in the cascode sections where voltage stress is highest, rather than throughout the entire signal path. This localized application maintains reliability where needed while preserving high speed operation in the critical signal amplification regions.
Solution Approach 2:
The amplifier is segmented into different functional sections with different transistor types: low voltage transistors for high-speed signal processing and high voltage transistors for voltage protection. This segmentation allows each section to be optimized for its specific function without compromising the other.
3Power
If cascoded transistors are used to increase DC gain, then DC voltage gain is improved, but output voltage swing is reduced
Solution Approach 1:
The patent changes the voltage parameters of the cascode transistors by using high voltage MOS devices with thicker gate oxide. This allows the cascode transistors to sustain higher voltages without breakdown, thereby increasing the available output voltage swing while maintaining the DC gain benefits of the cascode configuration.
Data Source
AI summary
A two-stage amplifier circuit fabricated in a dual gate oxide fabrication process having thick gate oxide devices as high voltage MOS transistors and thin gate oxide devices as low voltage MOS transistors includes a first stage amplifier and a second stage amplifier. The first stage amplifier receives a first pair of differential input voltages and provides a first pair of differential output voltages referenced to a first output common mode voltage. The second stage amplifier receives the first pair of differential output voltages of the first stage amplifier and provides a second pair of differential output voltages referenced to a second output common mode voltage. The first and second pair of input transistors are low voltage MOS transistors and the first output common mode voltage has a voltage value that is minimized to maximize the voltage swing of the second pair of differential output voltages.