Dual-Gate Oxide DRAM Cell for Low-Leakage Data Retention
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Solution Overview
Problem
In DRAM memory devices using oxide semiconductor transistors, the reliability is compromised when a high potential is applied to the back gate to influence electrical characteristics, leading to reduced data retention time and increased leakage current.
Innovation Solution
A memory device with a driver circuit that applies a first potential lower than the source and drain potential to the first gate and a second potential lower than the source and drain potential to the second gate, utilizing a metal oxide with In, Zn, and Ga in the channel formation region, which includes overlapping gates to enhance data retention and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high potential is applied to the back gate to influence electrical characteristics, then the transistor's electrical characteristics are improved, but the reliability is reduced and leakage current increases
Solution Approach 1:
The gate is divided into two separate gates: a front gate and a back gate. This segmentation allows independent control of the transistor's electrical characteristics (via back gate) and reliability (via front gate), resolving the contradiction by enabling separate optimization of both parameters without interference.
Solution Approach 2:
The back gate acts as an intermediary that influences the transistor's electrical characteristics indirectly through the substrate, rather than applying high potential directly to the channel. This mediation allows characteristic optimization while maintaining lower overall potential levels that preserve reliability and reduce leakage current.
2Reliability
If a high potential is applied to the back gate, then electrical characteristics are influenced, but data retention time is reduced
Solution Approach 1:
By segmenting the gate control into front and back gates, the patent enables independent optimization: the back gate enhances electrical characteristics while the front gate maintains appropriate potential levels during data retention periods, preventing excessive leakage that would reduce data retention time.
Solution Approach 2:
The back gate potential is applied periodically or selectively during specific operations (write, read, refresh) rather than continuously at high levels. This periodic application improves electrical characteristics when needed while minimizing the time during which high potential could reduce data retention.
3Reliability
If a high potential is applied to the back gate, then electrical characteristics are improved, but refresh frequency requirements increase
Solution Approach 1:
The segmented gate structure allows the back gate to enhance electrical characteristics independently, enabling the front gate to maintain lower potential levels that reduce leakage current. This reduces the frequency at which refresh operations are needed, improving productivity by lowering refresh frequency requirements.
Data Source
AI summary
A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.