Dual-Gate Oxide Memory Cell for Longer DRAM Data Retention
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Solution Overview
Problem
In DRAM memory devices using oxide semiconductor transistors, the reliability is compromised when a high potential is applied to the back gate to reduce the threshold voltage, leading to potential leakage currents and reduced data retention time.
Innovation Solution
A memory device design incorporating a driver circuit that applies distinct potentials to multiple gates of a transistor with a metal oxide channel, where one gate is driven to reduce off-state current and enhance reliability, using indium, zinc, and gallium-based metal oxides to manage the electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high potential is applied to the back gate to reduce the threshold voltage, then the transistor switching performance is improved, but leakage currents increase and reliability deteriorates
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate and second gate) that can be controlled separately. This allows independent optimization of different gate potentials to achieve both low threshold voltage (for switching performance) and low leakage current (for reliability) simultaneously, resolving the contradiction between switching performance and reliability.
Solution Approach 2:
Different regions of the gate structure are assigned different electrical characteristics and potentials. The first gate and second gate have distinct potential controls, enabling local optimization where one gate region manages threshold voltage while another manages leakage suppression, thus resolving the contradiction between switching performance and reliability.
2Speed
If a high potential is applied to the back gate, then the threshold voltage is reduced, but data retention time decreases
Solution Approach 1:
The gate is divided into multiple independently controllable segments (first gate and second gate), allowing separate control of threshold voltage (for speed) and data retention (for duration). This segmentation enables simultaneous optimization of both parameters without compromise.
Solution Approach 2:
The gate potentials are made dynamically adjustable through independent control of first and second gates. This dynamic control allows the system to optimize threshold voltage for fast switching while maintaining appropriate retention characteristics, resolving the contradiction between threshold voltage control and data retention time.
3Reliability
If distinct potentials are applied to multiple gates, then leakage currents are minimized and reliability is improved, but device complexity increases
Solution Approach 1:
While segmentation into multiple gates does increase structural complexity, it enables superior reliability through independent potential control. The segmentation allows each gate to be optimized for specific functions (threshold control, leakage suppression), achieving high reliability that compensates for the added complexity.
Solution Approach 2:
The multiple gate structure serves multiple functions simultaneously: threshold voltage control, leakage current suppression, and data retention optimization. This multi-functionality justifies the increased device complexity by delivering comprehensive performance improvements in a single integrated structure.
Data Source
AI summary
A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.