Dual-Gate Semiconductor Structure to Protect Tunneling Oxide
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cycling between programming and erasing operations in transistors deteriorates the tunneling oxide layer, leading to reduced device lifespan.
Innovation Solution
The semiconductor device includes a first terminal with a tunneling oxide layer and a first gate, and a second terminal with a second gate separated by a dielectric layer, allowing for erasing operations based on a voltage difference across the dielectric layer instead of the tunneling oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If erasing operations are performed using voltage difference across the tunneling oxide layer, then programming and erasing functions are achieved, but the tunneling oxide layer deteriorates and device lifespan is reduced
Solution Approach 1:
The gate structure is segmented into a control gate and a select gate, separated by a dielectric layer. This segmentation allows independent voltage application to each gate, enabling erasing operations to be performed across the dielectric layer rather than across the tunneling oxide layer, thus protecting the tunneling oxide from deterioration during erasure
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the control gate and select gate. This dielectric layer serves as the new medium for voltage difference application during erasing operations, replacing the tunneling oxide layer's role in erasure and preventing its deterioration
2Reliability
If multiple gates are separated by a dielectric layer, then stress on tunneling oxide is reduced, but device structure becomes more complex
Solution Approach 1:
The dielectric layer between the control gate and select gate serves multiple functions: it electrically isolates the two gates, enables independent voltage control for selective operations, and provides the erasure path without requiring additional protective layers. This multi-functionality reduces overall device complexity despite the added gate structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces stress on the tunneling oxide layer and minimizes deterioration during programming and erasing cycles, thereby extending the lifespan of the semiconductor device.
Implementation Method 1
a second dielectric layer formed between the first volume of polysilicon-based material and the second volume of polysilicon-based material
Data Source
AI summary
In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.