Dual-Gate Oxide Semiconductor Transistor Fabrication

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current oxide-semiconductor transistors lack flexibility in providing multiple threshold voltage (Vt) options and have insufficient Ion/Ioff performance, limiting their fabrication and structural improvements.

Innovation Solution

A method involving the formation of a channel layer, gate dielectric layer, source and drain layers, a bottom gate, phase change layer, and a top gate is employed, with specific materials and processes like high-k dielectric materials and phase change materials like germanium antimony telluride to enhance device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional oxide-semiconductor transistor structure is used, then the fabrication process is simple, but the device lacks flexibility in providing multiple threshold voltage options and has insufficient Ion/Ioff performance

Engineering Contradiction:
Improvemultiple Vt optionsVSAvoidtransistor structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The gate structure is segmented into a bottom gate and a top gate, separated by an insulating layer. This segmentation allows independent control of threshold voltage through the bottom gate and enhancement of Ion/Ioff characteristics through the top gate, thereby providing multiple Vt options while maintaining fabrication feasibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The top gate is formed within a recess of the insulating layer, creating a nested structure where the top gate is embedded in the insulating material. This nesting approach enables complex gate functionality without significantly increasing overall device footprint or fabrication complexity

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If a conventional oxide-semiconductor transistor structure is used, then the fabrication process is straightforward, but the Ion/Ioff performance is insufficient

Engineering Contradiction:
ImproveIon/Ioff performanceVSAvoidtransistor structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate is divided into bottom gate and top gate components that work together to achieve superior Ion/Ioff performance. The bottom gate provides threshold voltage control while the top gate enhances carrier accumulation, resulting in improved switching characteristics without overly complicating the fabrication process

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The transistor employs an oxide semiconductor film as the active layer, which inherently provides low leakage current. This composite material approach, combining oxide semiconductor with the dual-gate structure, achieves high Ion/Ioff performance while maintaining compatibility with existing fabrication techniques

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS10062734B2Method for fabricating a semiconductor device
Publication Date: 2018.08.28 UNITED MICROELECTRONICS CORP
  • US10062734B2 patent drawing
  • US10062734B2 patent drawing
  • US10062734B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer near one side of the gate dielectric layer and a drain layer near another side of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.