Dual-Gate Oxide TFT Layout for Simpler N/P Display Fabrication
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Solution Overview
Problem
The manufacturing process for flat panel display devices that include both N-type and P-type oxide semiconductor transistors is complicated due to the need for additional steps such as forming and removing passivation layers, which increases complexity and cost.
Innovation Solution
A thin film transistor (TFT) design is implemented with a bottom gate electrode, a semiconductor layer comprising both N-type and P-type semiconductor layers, where the N-type layer is partly overlapped with the P-type layer, and separate source and drain electrodes connected to each type, along with a top gate electrode, simplifying the manufacturing process by eliminating the need for additional passivation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If both N-type and P-type oxide semiconductor transistors are manufactured using conventional processes, then both transistor types can be produced, but the manufacturing process complexity increases due to additional passivation layer formation and removal steps
Solution Approach 1:
The patent combines the manufacturing processes for N-type and P-type oxide semiconductor transistors into a single integrated process. The dual-gate TFT structure allows both transistor types to be formed simultaneously without requiring separate passivation layer formation and removal steps, thereby reducing manufacturing process complexity while maintaining the ability to produce both transistor types.
Solution Approach 2:
The invention creates a universal TFT structure with dual gates that can function as either N-type or P-type transistor depending on the applied voltage polarity. The top gate and bottom gate can be independently controlled to achieve different transistor characteristics, making the same structural design applicable for both transistor types without requiring additional process steps.
2Reliability
If conventional manufacturing processes are used for both N-type and P-type transistors, then proper protection during patterning can be achieved, but production time and cost increase
Solution Approach 1:
The patent extracts and eliminates the unnecessary passivation layer formation and removal steps from the conventional manufacturing process. By using the dual-gate TFT structure with selective gate control, the invention achieves proper protection and isolation of semiconductor layers during patterning without requiring additional passivation layers, thereby reducing production time and process cost.
3Manufacturing precision
If separate manufacturing processes are used for N-type and P-type transistors, then each transistor type can be optimized, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the manufacturing processes for N-type and P-type transistors into a single dual-gate TFT fabrication process. The structure allows both transistor types to be formed using the same sequence of steps, including semiconductor layer formation, gate electrode deposition, and contact formation, thereby reducing the number of manufacturing processes while maintaining the ability to optimize each transistor type through independent gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the complexity of the manufacturing process, enhances efficiency, and allows for the production of both N-type and P-type semiconductor characteristics in a single TFT, improving the performance and cost-effectiveness of display devices.
Implementation Method 1
The N-type TFT and the P-type TFT may each be a metal oxide semiconductor field effect transistor (MOSFET) which controls a flow of a current with an electric field.
Data Source
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AI summary
Disclosed are a thin film transistor and a display device including the thin film transistor. The thin film transistor comprises: a bottom gate electrode on a substrate; a semiconductor layer overlapping with the bottom gate electrode, wherein the semiconductor layer comprises a N-type semiconductor layer and a P-type semiconductor layer, and the N-type semiconductor layer is overlapped partly with the P-type semiconductor layer; a first source electrode and a first drain electrode respectively connected to the P-type semiconductor layer; a second source electrode and a second drain electrode respectively connected to a portion of the N-type semiconductor layer which is not overlapped with the P-type semiconductor layer; and a top gate electrode above the semiconductor layer. According to the embodiment of the present disclosure, a complexity of a manufacturing process of the thin film transistor is reduced.