Dual-Gate Differential Power Amplifier With Neutralization Capacitors

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Solution Overview

Problem

Conventional differential power amplifiers in RF environments suffer from instability due to parasitic capacitances, which cannot be effectively addressed by multi-gate implementations as they prevent the connection of neutralization capacitors.

Innovation Solution

A dual-gate differential power amplifier circuit is designed with cross-coupled neutralization capacitors and multi-gate transistors, where the first differential power amplifier includes parallel branches with neutralization capacitors, and a second differential power amplifier is coupled in parallel with multi-gate transistors, reducing parasitic capacitances and improving stability and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional differential power amplifiers are used in RF environments, then the circuit can operate, but instability occurs due to parasitic capacitances

Engineering Contradiction:
ImprovestabilityVSAvoidparasitic capacitances
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies neutralization capacitors connected in parallel with the multi-gate transistor to convert the harmful effect of parasitic capacitances into a beneficial effect. The neutralization capacitors are specifically sized to cancel out the parasitic capacitances, transforming the instability caused by parasitic effects into improved stability and performance.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent changes the electrical parameters of the circuit by introducing neutralization capacitors with specific capacitance values that counterbalance the parasitic capacitances. This parameter adjustment allows the circuit to operate stably despite the inherent parasitic effects of the multi-gate transistor structure.

Inventive Principle:
Principle #35Parameter changes

2Power

If multi-gate transistors are used to reduce parasitic capacitances, then saturation output power and efficiency improve, but neutralization capacitors cannot be connected

Engineering Contradiction:
Improvesaturation output powerVSAvoidconnection complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent utilizes the multiple gates of the multi-gate transistor to create additional connection dimensions. By connecting neutralization capacitors between different gates and terminals of the multi-gate transistor, the patent overcomes the connection limitations while maintaining the power and efficiency benefits of the multi-gate structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If neutralization capacitors are added to cancel parasitic capacitances, then stability improves, but device complexity increases

Engineering Contradiction:
ImprovestabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the neutralization capacitor functions with the existing multi-gate transistor structure by strategically connecting the capacitors between the transistor's gates and terminals. This integration approach achieves parasitic cancellation while minimizing the increase in overall circuit complexity compared to using separate neutralization components.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250112602A1Multi-gate differential power amplifier
Publication Date: 2025.04.03 GLOBALFOUNDRIES US INC
  • US20250112602A1 patent drawing
  • US20250112602A1 patent drawing
  • US20250112602A1 patent drawing

AI summary

A differential power amplifier circuit, including: a first differential power amplifier including first and second cross-coupled neutralization capacitors; and a second differential power amplifier, coupled in parallel with the first differential power amplifier, including a plurality of multi-gate transistors.