Dual-Gate Display Panel Layout for Uniform Pixel Brightness

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Solution Overview

Problem

The increase in resolution of display panels leads to higher manufacturing costs due to the need for more source driver chips, and process variation causes uneven brightness due to differing coupling capacitances between the gate and drain of thin-film transistors in different pixel structures.

Innovation Solution

A dual-gate array substrate design where the source and drain of each pixel structure are sequentially arranged along the same direction, with overlapping areas of drains and gates adjusted to compensate for alignment errors during manufacturing, reducing differences in coupling capacitance and feed-through voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of source driver chips is increased to support higher resolution, then the display resolution is improved, but the manufacturing cost increases

Engineering Contradiction:
Improvedisplay resolutionVSAvoidmanufacturing cost
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the function of multiple source driver chips into a single source driver chip by designing a dual-gate array substrate where one gate line controls pixel structures across multiple columns. This integration reduces the number of source driver chips needed, thereby lowering manufacturing cost while maintaining high display resolution

Inventive Principle:
Principle #5Merging (Combining)

2Illumination intensity

If process variation is reduced to achieve uniform coupling capacitances, then brightness uniformity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvebrightness uniformityVSAvoidalignment precision
Core Design Contradiction:
Illumination intensityVSManufacturing precision

Solution Approach 1:

The patent changes the geometric parameters of the pixel structures, specifically arranging sources and drains sequentially along the same direction with optimized dimensions. The source and drain have widths of 1.5-2.0 μm and lengths of 3.0-5.0 μm, with specific overlapping areas with the gate. This parameter optimization makes the coupling capacitance less sensitive to alignment variations, achieving brightness uniformity without requiring extremely high manufacturing precision

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves brightness uniformity by ensuring consistent coupling capacitances and feed-through voltages across pixel structures, enhancing image quality.

Implementation Method 1

thin-film transistors in different pixel structures easily have different coupling capacitances between the gate and the drain

Methodology Applied
Scientific EffectCoupling capacitance: Capacitance

Data Source

PatentUS20260086412A1Display panel
Publication Date: 2026.03.26 HANNSTAR DISPLAY CORP
  • US20260086412A1 patent drawing
  • US20260086412A1 patent drawing
  • US20260086412A1 patent drawing

AI summary

A display panel is provided and includes a dual-gate array substrate, which includes a substrate, a plurality of gate lines, a plurality of data lines, and a plurality of pixel structures. The gate lines, the data lines, and the pixel structures are disposed on the substrate. Each of the pixel structures includes a thin film transistor and a pixel electrode. A gate, a source, and a drain of the thin film transistor are coupled to one of the gate lines, one of the data lines, and the pixel electrode, respectively. The source and the drain of each of the pixel structures are sequentially arranged along a same direction.