Dual Gate Electrode Patterning With Fewer Masks and CMP Margin

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The manufacturing of semiconductor devices with multiple gate electrodes requires precise dimensional control, leading to increased manufacturing costs due to the need for multiple masks. Additionally, aligning the heights of different conductive films while preventing the disappearance of parts of these films during polishing poses a technical challenge.

Innovation Solution

A method is developed to form a first conductive film on a semiconductor substrate, followed by patterning it to create a conductive pattern. A second conductive film is then formed with specific portions on the substrate and on the upper surface of the first conductive pattern. By selectively removing certain portions of the second conductive film, the method aligns the heights of the conductive films while minimizing the risk of film disappearance during polishing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple patterning steps are used to form gate electrodes with precise dimensional control, then manufacturing precision is improved, but device complexity and manufacturing cost increase due to increased number of masks

Engineering Contradiction:
Improvedimensional control of gate electrodesVSAvoidnumber of masks
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple patterning operations into a single patterning step by forming both the first gate electrode pattern and second gate electrode pattern simultaneously. This is achieved by forming a unified conductive film structure that includes both gate electrode regions, allowing one patterning step to define both patterns rather than requiring separate patterning steps for each gate electrode type.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductive film is segmented into different functional regions (first conductive film for high-speed MOSFET gate electrode, second conductive film for low-leakage MOSFET gate electrode) with different heights, where the third portion connects these segments. This segmentation allows different gate electrode types to be formed from the same continuous conductive film structure through selective removal.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If CMP polishing is used to flatten the upper surfaces of conductive films, then manufacturing precision is improved by eliminating steps, but reliability deteriorates due to risk of second conductive film disappearance

Engineering Contradiction:
Improveflatness of upper surfacesVSAvoidintegrity of second conductive film
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The conductive film structure has different local qualities (heights) in different regions: the first portion and second portion are at different heights relative to the third portion. This local height variation allows the upper surface to be flattened by CMP polishing while the third portion extends higher and protects the second conductive film from being completely removed, ensuring selective preservation of critical film regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The third portion of the conductive film acts as a protective cushion that extends higher than the first and second portions. This pre-formed higher region serves as a buffer that prevents the second conductive film from being completely removed during CMP polishing, as the third portion is removed first, cushioning the underlying second conductive film from excessive polishing damage.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20250169137A1Method of manufacturing semiconductor device
Publication Date: 2025.05.22 RENESAS ELECTRONICS CORP
  • US20250169137A1 patent drawing
  • US20250169137A1 patent drawing
  • US20250169137A1 patent drawing

AI summary

A first conductive pattern is formed on a semiconductor substrate and formed from a first conductive film. A second conductive film having a first portion on the semiconductor substrate, a second portion on an upper surface of the first conductive pattern, and a third portion connecting the first portion and the second portion so as to cover a side surface of the first conductive pattern, is formed. The upper surface of the third portion is higher than the upper surface of the first portion. The second portion is patterned. The second portion and a part of the third portion are selectively removed. By patterning the first conductive pattern and the second conductive film, a first gate electrode is formed from a part of the first conductive pattern, and a second gate electrode is formed from a part of the first portion.