Dual-Gate Pixel Structure With Trace-Length Capacitance Matching

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Solution Overview

Problem

In dual-gate pixel driving structures, the mismatch in capacitance between adjacent pixel units due to different distances from data lines leads to non-uniform brightness and poor display quality, while attempts to match capacitance by placing thin film transistors between pixels reduce pixel opening ratio and symmetry.

Innovation Solution

A pixel structure where the first and second pixel units are arranged with their thin film transistors and connecting traces on one side of the data line, ensuring matching capacitance between adjacent units without occupying pixel electrode area, thus improving symmetry and opening ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two adjacent pixel units are connected to the same data line and arranged on the same side of the data line, then the polarity issue is improved and display quality is enhanced, but the distances of the two pixel units to the data line become unequal, causing capacitance mismatch and non-uniform brightness distribution

Engineering Contradiction:
Improvedisplay qualityVSAvoidcapacitance uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the connecting traces have different lengths to compensate for the unequal distances of pixel units to the data line. Specifically, the pixel unit farther from the data line has a longer connecting trace, while the closer pixel unit has a shorter connecting trace, thereby equalizing the total capacitance for both pixel units despite their different positions.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If a thin film transistor is arranged between two pixel units to achieve capacitance matching, then capacitance uniformity is improved, but the pixel opening ratio is reduced and pixel electrode symmetry is compromised

Engineering Contradiction:
Improvecapacitance uniformityVSAvoidpixel opening ratio
Core Design Contradiction:
Manufacturing precisionVSArea of moving object

Solution Approach 1:

The patent resolves the contradiction by moving the capacitance matching mechanism from the spatial dimension (placing transistors between pixels) to the trace length dimension. The connecting traces are designed with different lengths to compensate for position differences, achieving capacitance matching without occupying pixel electrode space or compromising symmetry.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Area of moving object

If the first pixel electrode is set closer to the data line than the second pixel electrode, then the pixel opening ratio is improved and electrode symmetry is enhanced, but the distances to the data line become unequal, requiring capacitance compensation

Engineering Contradiction:
Improvepixel opening ratioVSAvoidcapacitance matching
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the length parameter of the connecting traces to compensate for the unequal distances of pixel electrodes to the data line. The connecting trace lengths are specifically designed to equalize the total capacitance, allowing the pixel electrodes to be positioned asymmetrically relative to the data line while maintaining capacitance uniformity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4016177B1Pixel structure, array substrate, and display panel
Publication Date: 2024.10.23 HKC CORP LTD
  • EP4016177B1 patent drawingFigure 1
  • EP4016177B1 patent drawingFigure 2
  • EP4016177B1 patent drawingFigure 3

AI summary

The present application discloses a pixel structure, an array substrate and a display panel. The pixel structure includes a first data line (D1); a first gate line (G1) and a second gate line (G2); a first pixel unit (10) and a second pixel unit (20). The first pixel unit (10) and second pixel unit arranged along a second direction; a first pixel electrode (11) of the first pixel unit (10) is closer to the first data line (D1) than a second pixel electrode (21) of the second pixel unit (20), a first thin film transistor (12) of the first pixel unit (10) and second thin film transistor (22) of the second pixel unit (20) are arranged close to the first data line; a first connecting trace (30) is set between the first drain electrode (123) and the first pixel electrode (11), a second connecting trace (40) is set between the second drain electrode (223) and the second pixel electrode (21) to make a capacitance of the first pixel unit matching with a capacitance of the second pixel unit.