Dual-Gate Polysilicon Transistor with Integrated Capacitor
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Solution Overview
Problem
Current organic light emitting displays face challenges in achieving fast driving times and high light emitting efficiency due to limitations in transistor design and manufacturing processes, particularly in the formation of polysilicon layers and capacitors.
Innovation Solution
A transistor design featuring a polysilicon layer with a channel region and ion doping regions, where the grains in the channel region are larger than in the ion doping regions, and a dual gate electrode structure that also serves as a capacitor, allowing for efficient control of driving current and reducing manufacturing complexity by eliminating the need for a separate capacitor area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional transistor design with separate capacitor area is used, then the capacitor can be formed independently, but the opening portion area is reduced and manufacturing complexity increases
Solution Approach 1:
The patent combines the capacitor function with the gate electrode structure by forming the capacitor between the first gate electrode and the second gate electrode. This integration eliminates the need for a separate capacitor area, thereby increasing the opening portion area while simplifying the manufacturing process by reducing the number of discrete components.
Solution Approach 2:
The gate electrode structure serves dual functions: as the control electrode for the transistor and as one of the capacitor electrodes. This multi-functionality allows the same structural element to perform both switching control and charge storage functions, reducing overall device complexity and increasing active area.
2Speed
If the polysilicon layer is formed without optimized grain structure, then the manufacturing process is simpler, but the transistor driving speed is slower
Solution Approach 1:
The patent implements different grain sizes in different regions of the polysilicon layer: larger grains (30-40 micrometers) in the channel region for high-speed operation, and smaller grains (10-20 micrometers) in the ion doping regions for proper electrical characteristics. This local differentiation optimizes both driving speed and manufacturing feasibility.
Solution Approach 2:
The patent controls the polysilicon grain size by adjusting laser irradiation parameters during the polysilicon formation process. By modifying laser power, scanning speed, and irradiation patterns, the desired grain size distribution is achieved, enabling fast transistor operation without excessive manufacturing complexity.
3Productivity
If the channel region has small grain size, then the manufacturing process is easier, but the light emitting efficiency is reduced
Solution Approach 1:
The patent creates a localized region of large grains specifically in the channel area where high light emitting efficiency is critical, while maintaining smaller grains in the ion doping regions. This spatial variation in grain quality maximizes optical performance without compromising manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the driving speed of transistors and improves light emitting efficiency by increasing the size of the polysilicon grains and optimizing the capacitor structure, thereby reducing manufacturing time and increasing the opening portion for improved performance.
Implementation Method 1
irradiating a laser to the amorphous silicon layer from a lower portion of the base substrate to form a polysilicon layer from the amorphous silicon layer
Implementation Method 2
ion-doping a portion of the polysilicon layer using the second gate electrode as a mask to form a first ion doping region and a second ion doping region
Data Source
AI summary
A transistor including a polysilicon layer on a base substrate and including a channel region, a first ion doping region, a second ion doping region, the channel region being between the first and second ion doping regions, an average size of the grains in the channel region being greater than that of the grains in the first and second ion doping regions, a first gate electrode insulated from and overlapping the channel region, a second gate electrode insulated from the first gate electrode and overlapping the channel region, an inter-insulating layer on the second gate electrode, a source electrode on the inter-insulating layer and connected to the first ion doping region, and a drain electrode on the inter-insulating layer and connected to the second ion doping region.