Dual-Gate Power Supply Circuit for Wideband PSRR
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Solution Overview
Problem
Existing power supply circuits, particularly for image sensors, suffer from inadequate power supply rejection ratio (PSRR) and frequency limitations, leading to noise interference that degrades image quality.
Innovation Solution
A power supply circuit with a closed regulation loop and dual-gate transistors, where one gate is controlled by a sampled reference voltage and the other by a closed regulation loop, enhances PSRR by using transistors with different transconductances and capacitances to stabilize the circuit and reduce noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing power supply circuits are used, then the circuit structure is simple, but the power supply rejection ratio (PSRR) is inadequate and frequency range is limited
Solution Approach 1:
The power supply circuit is segmented into multiple transistor devices (first transistor device with first and second gates, second transistor device with third and fourth gates), each with different transconductances. This segmentation allows independent optimization of each segment's function, achieving high PSRR across wide frequency range while maintaining manageable circuit complexity through modular architecture
Solution Approach 2:
The circuit employs dynamic control through closed regulation loop that continuously adjusts the transistor gates based on feedback. The regulator dynamically balances the contribution of different transistor devices with varying transconductances, enabling the circuit to adaptively maintain high PSRR across changing frequency conditions without requiring overly complex static circuit design
2Object-affected harmful factors
If existing power supply circuits are used, then the circuit design is straightforward, but noise interference degrades image quality
Solution Approach 1:
Different transistor devices are assigned different transconductance values (gms1, gms2, gms3, gms4) to create local quality variations within the circuit. This allows specific regions of the circuit to be optimized for different frequency ranges and noise rejection functions, effectively reducing noise interference at pixel level while keeping the overall device configuration organized and manageable
Solution Approach 2:
A closed regulation loop with regulator is implemented to provide continuous feedback control. The regulator monitors the output and adjusts the transistor gate voltages accordingly, creating a self-correcting system that actively reduces noise interference. This feedback mechanism achieves superior noise rejection without requiring excessively complex circuit topology
3Adaptability or versatility
If existing power supply circuits are used, then external decoupling capacitors are required, but this increases device complexity and limits frequency range
Solution Approach 1:
The circuit design extracts and eliminates the need for external decoupling capacitors by integrating all necessary filtering and stabilization functions within the transistor device configuration itself. The multiple transistor devices with different transconductances work together to provide inherent frequency compensation, achieving wide frequency range adaptability (up to 10 MHz and beyond) without external components that would increase device complexity
Solution Approach 2:
The transistor devices serve multiple functions simultaneously: they provide power supply regulation, noise filtering, frequency compensation, and stabilization across wide frequency ranges. This multi-functionality eliminates the need for separate external decoupling capacitors and other auxiliary components, reducing overall device complexity while enhancing adaptability to different frequency requirements
Data Source
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AI summary
The present description concerns a power supply circuit (300, 500, 600) comprising a first transistor device (MLOOP, MLOOP1, MLOOP2) comprising a first gate (310) associated with a first transconductance and a second gate (308) associated with a transconductance greater than the first transconductance; a second transistor device (MVRT, MVRT1, MVRT2) comprising a third gate (304) associated with a second transconductance and a fourth gate (302) associated with a transconductance greater than the second transconductance; the first and the third gates (310, 304) being controlled by a closed regulation loop; the second and the fourth gate (308, 302) being controlled by a sampled reference voltage (VGVRT); the second transistor device (MVRT, MVRT1, MVRT2) being capable of powering at least one load (20) .