Dual-Gate RF Cell Layout for Lower Parasitic Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
RF circuits face limitations in layout design due to increased parasitic capacitance and resistance from smaller metal wires and vias, restricting the freedom of circuit layouts, especially in middle-end-of-line layers using double-patterning technology, which hampers the scaling of transistors in low noise amplifiers and voltage-controlled oscillators.
Innovation Solution
The proposed solution involves a dual-gate design for RF circuits where gates are disposed across an active region with specific via arrangements, allowing two transistors to connect in a cascoded configuration, reducing parasitic resistance and capacitance by optimizing gate contact arrangements and metallization layer connections, enabling compact and scalable RF circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If smaller metal wires and vias are used to scale transistors, then transistor scaling is achieved, but parasitic capacitance and resistance increase
Solution Approach 1:
The patent transitions from planar gate contacts to vertical 3D U-shaped gate contacts that wrap around the channel region. This dimensional change allows gate control from multiple directions (top, bottom, and sides) rather than just from above, effectively reducing parasitic capacitance and resistance while maintaining scaled transistor dimensions.
Solution Approach 2:
The U-shaped gate structure nests the gate contact within the channel region by extending gates from both sides and connecting them at the bottom. This nested configuration maximizes gate control over the channel while minimizing the footprint and reducing parasitic effects from external connections.
2Manufacturing precision
If double-patterning technology is used in MEOL layers, then manufacturing precision is improved, but layout freedom is restricted
Solution Approach 1:
The gate contact is segmented into multiple parts: top gates extending from left and right sides, and a bottom gate connecting them. This segmentation allows each part to be independently optimized for the double-patterning process while maintaining overall layout flexibility. The segmented structure can be fabricated using standard photolithography and etching steps.
Solution Approach 2:
The U-shaped gate contact design serves multiple functions: it provides gate control from multiple directions, reduces parasitic effects, maintains compatibility with double-patterning manufacturing, and enables flexible layout configurations. This multi-functional design resolves the conflict between manufacturing precision requirements and layout freedom.
3Ease of manufacture
If conventional gate contact arrangements are used, then manufacturing simplicity is maintained, but parasitic resistance and capacitance increase
Solution Approach 1:
The gate contacts are extended from the sides to overlap with the channel region before the final connection is made. This preliminary extension allows the gates to establish control over the channel early in the formation process, reducing parasitic capacitance that would otherwise exist from non-overlapping configurations. The overlapping structure is created through standard extension and etching steps.
Data Source
AI summary
A cell layout design for an integrated circuit. In one embodiment, the integrated circuit includes a dual-gate cell forming two transistors connected with each other via a common source/drain terminal. The dual-gate cell includes an active region, two gate lines extending across the active region, at least one first gate via disposed on one or both of the two gate lines and overlapped with the active region, and second gate vias disposed on one or both of the two gate lines and located outside the active region.