Dual-Gate Transistor Arrays for Low-Voltage RRAM Scaling
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Solution Overview
Problem
The scalability of resistive random-access memory devices is limited by the voltage and drive current requirements of field-effect transistors, restricting the ability to shrink their dimensions.
Innovation Solution
A structure comprising a dielectric layer on a substrate with pairs of field-effect transistors, where each pair shares a gate electrode and has semiconductor layers connected between them, allowing independent biasing of wells for reduced operating voltages and enhanced scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If field-effect transistors are shrunk to improve integration density, then device size is reduced, but voltage and drive current requirements cannot be met
Solution Approach 1:
The transistor gate is segmented into two independent gates (first gate electrode and second gate electrode) that can be biased independently. This segmentation allows separate control of channel formation and threshold voltage, enabling sufficient drive current and voltage control even in scaled-down devices, thus resolving the contradiction between small size and reliable operation.
Solution Approach 2:
The invention changes the electrical parameters by applying different bias voltages to the two gates independently. The first gate controls channel formation while the second gate adjusts threshold voltage, allowing optimization of both drive current and operating voltage separately. This parameter control enables small transistors to meet voltage and drive current requirements through independent gate biasing.
2Productivity
If transistor dimensions are reduced to increase integration density, then device scalability is improved, but operating voltage requirements cannot be satisfied
Solution Approach 1:
By segmenting the gate into two independently biasable electrodes, the invention enables separate optimization of channel conductivity (first gate) and threshold voltage (second gate). This allows small transistors to achieve sufficient drive current through first gate biasing while maintaining appropriate threshold voltage through second gate biasing, thus enabling low-voltage operation at high integration density.
Solution Approach 2:
Independent biasing of the two gates allows dynamic adjustment of electrical parameters to optimize power consumption. The first gate can be biased to maximize channel conductivity for low resistance, while the second gate can be biased to set an optimal threshold voltage, enabling the transistor to operate efficiently at lower voltages despite reduced dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure enables reduced operating voltages and improved scalability of resistive random-access memory devices by allowing independent control over gate electrodes, facilitating smaller transistor dimensions and increased integration density.
Implementation Method 1
Field-effect transistors are commonly used as access transistors in a resistive random-access memory device
Data Source
AI summary
Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.