Display Scan Driver Dual-Gate Voltage Control for Reduced Power
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Solution Overview
Problem
Existing display apparatuses face challenges in reducing power consumption while maintaining image quality and functionality, particularly due to inefficiencies in gate voltage control for transistors.
Innovation Solution
The display apparatus employs a dual-gate voltage system with separate gate voltages for n-type and p-type MOSFETs, along with synchronized clock signals, to optimize transistor switching and reduce unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a single gate voltage is used for both n-type and p-type MOSFETs, then the device complexity is reduced, but power consumption cannot be optimized
Solution Approach 1:
The gate voltage control system is segmented into separate voltage sources: a first gate voltage for n-type MOSFETs and a second gate voltage for p-type MOSFETs. This segmentation allows independent optimization of voltages for each transistor type, reducing power consumption while maintaining manageable system complexity through modular voltage generation circuits.
Solution Approach 2:
Different gate voltages are applied to different transistor types based on their specific requirements. N-type MOSFETs receive a first gate voltage optimized for their operation, while p-type MOSFETs receive a second gate voltage optimized for their operation. This local quality approach ensures each component receives the precise control it needs, improving overall power efficiency.
2Use of energy by moving object
If separate gate voltages are applied to n-type and p-type MOSFETs, then power consumption is reduced, but the device complexity increases
Solution Approach 1:
The separate gate voltage generation circuits are merged into an integrated driver circuit that outputs both the first gate voltage and second gate voltage simultaneously. This merging approach provides the necessary separate voltages for optimal transistor control while consolidating the complexity into a single integrated component, balancing power optimization with system manageability.
Solution Approach 2:
The gate voltage control system dynamically adjusts the first and second gate voltages based on operational requirements. The driver circuit can independently control the timing and magnitude of voltages applied to n-type and p-type MOSFETs, enabling adaptive power management that reduces consumption during low-activity periods while maintaining performance when needed.
3Productivity
If gate voltages are not synchronized with clock signals, then the control system is simpler, but transistor switching efficiency decreases
Solution Approach 1:
The gate voltages are applied in periodic synchronization with clock signals. The first gate voltage is activated in sync with clock edges to control n-type MOSFET switching, and the second gate voltage is activated in sync with clock edges to control p-type MOSFET switching. This periodic synchronization ensures optimal switching timing, improving productivity while the regular rhythm simplifies control compared to arbitrary timing schemes.
Solution Approach 2:
The clock signals provide a feedback mechanism that coordinates gate voltage application with the operational state of transistors. The synchronized timing ensures that gate voltages are applied at the optimal moment in the switching cycle, improving efficiency. The feedback from clock edges allows the driver circuit to automatically adjust voltage timing without complex control logic.
Data Source
AI summary
A display apparatus includes a pixel, a first scan driving circuit that transmits a first scan signal to the pixel based on a first gate voltage, a second gate voltage having a level lower than a level of the first gate voltage, and a first clock signal, and a second scan driving circuit that transmits a second scan signal to the pixel based on a third gate voltage having a level different from the level of the first gate voltage, a fourth gate voltage having a level lower than the level of the third gate voltage, and a second clock signal.