Dual-Gate SCR Structure for Low Trigger and Higher Holding Voltage
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Solution Overview
Problem
The decreasing breakdown voltage of gate oxide layers in semiconductor transistors limits ESD design windows, leading to high latch-up risks in silicon controlled rectifiers due to their low holding voltage and strong hysteresis characteristics, which are exacerbated by the slower decrease in chip operating voltage compared to breakdown voltages.
Innovation Solution
The integration of GGNMOS and GDPMOS within a silicon controlled rectifier structure, where the P+N and N+P junctions are subjected to avalanche breakdown, allowing for superimposed current flows that increase voltage change rates and reduce trigger voltage, while adjusting conduction paths to enhance holding voltage and reduce latch-up risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GGNMOS or GDPMOS is embedded in SCR to reduce trigger voltage, then the trigger voltage decreases, but the holding voltage remains low leading to high latch-up risk
Solution Approach 1:
The patent divides the conduction path into multiple segments by introducing separate GGNMOS and GDPMOS triggering paths. The GGNMOS handles electron injection while GDPMOS handles hole injection, segmenting the triggering mechanism to achieve independent control of trigger voltage and holding voltage characteristics.
Solution Approach 2:
The patent combines GGNMOS and GDPMOS structures within a single SCR device to create a composite structure that leverages both n-type and p-type MOS characteristics. This composite approach enables simultaneous reduction of trigger voltage through dual-gate control while maintaining higher holding voltage through coordinated conduction paths.
2Adaptability or versatility
If the ESD design window is narrowed due to decreasing gate oxide breakdown voltage, then material selection is limited, but the operating voltage cannot be reduced proportionally
Solution Approach 1:
The patent introduces dynamic control capabilities through GGNMOS and GDPMOS gates that can actively modulate the SCR triggering characteristics. This dynamic control allows the device to adapt its ESD protection behavior based on operating conditions, compensating for the narrowed design window and enabling broader material compatibility.
Solution Approach 2:
The patent enables independent adjustment of trigger voltage and holding voltage parameters through the dual-MOS gate structure. By changing gate voltages and conduction path characteristics, the device can optimize its ESD protection parameters without being constrained by the traditional breakdown voltage limitations of gate oxide layers.
3Strength
If SCR is used as ESD protection device, then robustness per unit area is improved, but the strong hysteresis leads to low holding voltage
Solution Approach 1:
The patent introduces GGNMOS and GDPMOS as intermediary control elements between the external circuit and the SCR conduction path. These intermediary MOS devices control the triggering and holding characteristics, allowing the robust SCR structure to be utilized while mitigating its inherent low holding voltage issue through active gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the trigger voltage and increases the holding voltage of the silicon controlled rectifier, facilitating the production of low voltage triggering silicon controlled rectifiers with adjustable trigger voltages and improved ESD protection by managing current flows and structural adjustments.
Implementation Method 1
The GGNMOS accelerates the triggering process for the SCR, and such a new structure is named as an N-type low voltage triggering silicon controlled rectifier (NLVTSCR)
Implementation Method 2
adjust the holding voltage by shunting conduction paths to manage current flow
Data Source
AI summary
The present application discloses a low voltage triggering silicon controlled rectifier which includes: an N well and a P well forming a PN junction, a first P+ region formed in the N well and connected to an anode, and a first N+ region formed in the P well and connected to a cathode. A second P+ region is formed in the N well at the PN junction and diffuses into the P well. A second N+ region is formed in the P well at the PN junction and diffuses into the N well. A first gate structure connected to the anode is formed at the surface of the N well between the first and second P+ regions; and a second gate structure connected to the cathode is formed at the surface of the P well between the first and second N+ regions.