Dual Gate Semiconductor Device for HCI Damage Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges with hot carrier injection (HCI) damage, especially in submicron technology platforms, leading to transconductance and linear current degradation, which are exacerbated by high operational voltages and are not compatible with current processing techniques.
Innovation Solution
A dual gate semiconductor device structure is implemented, where a first gate serves as a channel region and a second gate acts as an extended drain, with a separation region between them, reducing the maximum electric field and minimizing HCI damage through self-aligned construction using CMOS processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an extended drain with silicide block is formed to minimize HCI, then HCI damage is reduced, but transconductance degradation and linear current degradation occur due to charge trapped in the silicide block
Solution Approach 1:
The invention extracts and removes the silicide block from the extended drain structure. By eliminating the silicide block that causes charge trapping, the patent prevents transconductance degradation while maintaining the extended drain's ability to reduce HCI damage through its lightly-doped drift region
Solution Approach 2:
The invention introduces a lightly-doped drift region as an intermediary between the gate and drain. This drift region acts as a mediator that reduces the maximum electric field and minimizes HCI damage without requiring a silicide block, thereby avoiding the charge trapping problem that causes transconductance degradation
2Object-affected harmful factors
If doping within the drift region is reduced to improve extended drain performance, then HCI damage is minimized, but parasitic resistance increases
Solution Approach 1:
The invention optimizes the doping concentration parameter within the drift region to achieve a balance between HCI protection and resistance management. By carefully controlling the doping level in the extended drain structure, the patent minimizes HCI damage while preventing excessive parasitic resistance that would result from extremely low doping
3Productivity
If device size is reduced to increase packing density, then productivity is improved, but HCI problems are exacerbated due to maintained operational voltages
Solution Approach 1:
The invention segments the drain structure into an extended drain region with a lightly-doped drift region. This segmentation allows the device to maintain smaller dimensions for higher packing density while the extended drain segment provides HCI protection by reducing the maximum electric field, even at submicron scales with maintained operational voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual gate structure significantly reduces HCI damage, improves current carrying capability, and maintains performance while reducing device size, with the second gate acting as a protective device to limit voltage drop on the first gate, thus enhancing HCI immunity and matching performance.
Implementation Method 1
reducing the maximum electric field and minimizing HCI damage
Implementation Method 2
HCI occurs when electrons, or holes, are accelerated by a strong electric field and gain very high kinetic energies within a semiconductor device
Data Source
AI summary
A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions.