Dual-Gate Semiconductor Device Reducing Leak Current
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Solution Overview
Problem
Conventional semiconductor devices fail to simultaneously reduce leak current and increase ON current due to the overlapping of the second light-shielding film with the channel and impurity regions, leading to increased OFF leak current.
Innovation Solution
A semiconductor device with a top gate electrode, a bottom gate electrode, and a semiconductor layer having source, drain, and low-concentration impurity regions, where the bottom gate electrode overlaps the channel and adjacent impurity regions, and is controlled to maintain a prescribed potential, allowing for reduced leak current while increasing ON current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the second light-shielding film is used as the bottom gate electrode to increase ON current, then the ON current is increased, but the leak current increases due to overlapping with the channel and impurity regions
Solution Approach 1:
The invention divides the bottom gate structure into two separate gates: a first gate electrode positioned over the channel region and a second gate electrode positioned over the impurity regions. This segmentation allows independent control of the channel and impurity regions, enabling the first gate to enhance ON current while the second gate suppresses leak current without the harmful overlapping effect of a single integrated bottom gate electrode.
Solution Approach 2:
The invention applies different gate control strategies to different regions of the semiconductor device. The first gate electrode applies a first potential to the channel region to optimize carrier flow and increase ON current, while the second gate electrode applies a second potential to the impurity regions to suppress carrier generation and reduce leak current. This local quality approach allows optimized performance in each region without compromise.
2Power
If the bottom gate electrode overlaps the entire low-concentration impurity region, then the ON current is increased, but the vertical electric field in overlapping regions increases the OFF leak current
Solution Approach 1:
The invention segments the bottom gate function into two separate gate electrodes with distinct positioning and control. The first gate electrode is positioned to overlap the channel region for ON current enhancement, while the second gate electrode is positioned to overlap the impurity regions for leak current suppression. This segmentation eliminates the conflicting requirements of a single overlapping gate.
Solution Approach 2:
The invention changes the potential parameters applied to different gate electrodes independently. By applying a first potential to the first gate electrode and a second potential to the second gate electrode, the invention optimizes the electric field distribution to simultaneously achieve high ON current and low OFF leak current, resolving the contradiction caused by uniform potential application in conventional designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device effectively reduces leak current and increases ON current, enabling high-performance active matrix substrates and display devices with low power consumption.
Implementation Method 1
the bottom gate electrode is arranged so as to overlap the channel region, part of the low-concentration impurity region adjacent to the source region, and part of the low-concentration impurity region adjacent to the drain region, and wherein the bottom gate electrode is controlled to have a prescribed potential
Data Source
AI summary
A switching element (a semiconductor device) (18) having a top gate electrode (21) and a bottom gate electrode (23) is provided with a silicon layer (a semiconductor layer) (SL) that is arranged between the top gate electrode (21) and the bottom gate electrode (a light-shielding film) (23) and that has a source region (24), a drain region (28), a channel region (26), and low-concentration impurity regions (25, 27). Furthermore, the bottom gate electrode (23) is arranged so as to overlap the channel region (26), a part of the low-concentration impurity region (25), which is adjacent to the source region (24), and a part of the low-concentration impurity region (27), which is adjacent to the drain region (28). The bottom gate electrode (23) is controlled so as to have a prescribed potential.