Dual-Gate Semiconductor Device Leakage Current Control
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in scaling down dimensions while maintaining quality, yield, performance, and reliability, as well as reducing complexity, which existing technologies struggle to achieve effectively.
Innovation Solution
A semiconductor device design featuring a substrate with multiple gate structures, including a bottom gate and top gate configuration, where the conductive status of the channel layer is controlled by both gate structures, and the top gate dielectric and bottom gate dielectric have different thicknesses to provide distinct threshold voltages and functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single gate structure is used in conventional transistors, then the device structure is simple and easy to manufacture, but the control over channel conductivity is insufficient leading to higher leakage current
Solution Approach 1:
The transistor gate is segmented into two independent gate structures: a bottom gate structure and a top gate structure. Each gate can independently control the channel conductivity, providing dual control capability that reduces leakage current while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The gate control is extended from a single-plane configuration to a three-dimensional arrangement with bottom and top gates separated by vertical distance. This dimensional change enables independent control of channel conductivity from both above and below, improving leakage current control without excessive complexity increase
2Adaptability or versatility
If uniform gate dielectric thickness is used, then the manufacturing process is simpler, but the threshold voltage control and device applicability are limited
Solution Approach 1:
The gate dielectric layer is designed with non-uniform thickness: the first gate dielectric at the bottom gate has a different thickness than the second gate dielectric at the top gate. This local variation in dielectric thickness enables independent threshold voltage tuning for each gate, enhancing device adaptability while the thickness difference is controlled within manufacturing capabilities
Solution Approach 2:
The dielectric thickness parameter is changed between the bottom and top gates to achieve different threshold voltages. By adjusting the thickness of the first gate dielectric relative to the second gate dielectric, the invention enables versatile threshold voltage control for different application requirements
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first region, and a first transistor positioned in the first region. The first transistor includes a first bottom gate structure positioned on the substrate, a first channel layer positioned on the first bottom gate structure, a first top gate structure positioned on the first channel layer, and two first source/drain regions positioned on two sides of the first channel layer.