Dual-Gate Semiconductor Structure for Leakage Control
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Solution Overview
Problem
As DRAM devices are scaled down, achieving higher drain saturation current (Idsat) and lower off-leakage current (Idoff) becomes crucial for faster charging and lower power consumption, but existing semiconductor structures face limitations in increasing Idsat and reducing Idoff due to restricted channel length and current leakage.
Innovation Solution
A semiconductor structure with a dual-channel region formed by a bottom gate portion, a top gate portion, and a channel layer sandwiched between them, allowing for improved gate control and reduced current leakage by embedding the bottom gate deeper into the substrate, while maintaining increased Idsat and reduced Idoff.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the device size is reduced to achieve high integration and high density, then the memory cell layout becomes smaller, but the drain saturation current (Idsat) decreases and off-leakage current (Idoff) increases
Solution Approach 1:
The gate structure is segmented into a bottom gate portion and a top gate portion, forming a dual-gate configuration. This segmentation allows independent optimization of each gate's function: the bottom gate controls channel formation and the top gate enhances current modulation, thereby maintaining high Idsat and low Idoff even in scaled-down devices
Solution Approach 2:
The gate structure transitions from a single-plane gate to a three-dimensional stacked configuration with bottom and top gates separated by a channel layer. This dimensional change enables better electrostatic control and increased gate effectiveness without increasing the lateral footprint of the device
2Reliability
If the channel length is increased to reduce off-leakage current (Idoff), then the gate control ability improves, but the device area increases
Solution Approach 1:
The channel is configured as a vertically stacked layer between bottom and top gates rather than a horizontal extension. This vertical arrangement provides enhanced gate control and reduced leakage current through improved electrostatic field distribution without increasing the lateral device area
3Reliability
If the bottom gate is embedded deeper in the substrate to reduce current leakage, then the off-leakage current (Idoff) decreases, but the manufacturing complexity increases
Solution Approach 1:
The gate system is divided into bottom and top portions with distinct functions and fabrication sequences. The bottom gate is formed first through selective epitaxial growth and patterning, followed by channel layer deposition and top gate formation, allowing optimized control of current leakage through structured manufacturing steps
Data Source
AI summary
The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.