Dual Gate Semiconductor Fabrication with Threshold Voltage Control
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Solution Overview
Problem
Conventional semiconductor device fabrication methods struggle to achieve a wide range of threshold voltages for dual gates, limiting the operating speed and scalability of semiconductor devices.
Innovation Solution
A method involving the sequential formation of a gate insulation layer, a first capping layer, and a barrier layer across distinct regions on a substrate, followed by thermal processing to alter the composition of the gate insulation layers, allowing for different threshold voltages in each region using high-k materials and metal gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fabrication methods are used to form dual gates, then the manufacturing process becomes complex, but the threshold voltage variety remains limited
Solution Approach 1:
The patent applies preliminary action by forming a uniform gate insulation layer across both first and second regions before any differentiation occurs. This initial uniform structure simplifies the fabrication process, and subsequent selective material removal and deposition steps then create the desired dual gate configurations with different threshold voltages without requiring complex simultaneous patterning
Solution Approach 2:
The patent segments the gate structure into distinct first and second regions with different material compositions. By selectively removing the barrier layer and first capping layer from the first region while retaining them in the second region, the patent creates two separately controllable gate structures that can be independently tuned to different threshold voltages
2Speed
If high-k materials and metal gate electrodes are used, then the operating speed increases, but the fabrication process complexity increases
Solution Approach 1:
The patent utilizes parameter changes by selecting specific high-k materials (such as hafnium oxide, hafnium silicon oxide, or hafnium oxynitride) with dielectric constants greater than silicon oxide, and combining them with metal gate electrode materials. This material parameter selection enables higher operating speeds while the sequential fabrication approach keeps the process manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process while enabling a large variety in threshold voltages, enhancing the operating speed and scalability of semiconductor devices by forming dual gates with distinct insulation and electrode compositions.
Implementation Method 1
thermally processing the substrate on which the second capping layer is formed. As a result of the thermal processing, material of the second capping layer spreads into the gate insulation layer in the first region, and material of the first capping layer spreads into the gate insulation layer in the second region
Data Source
AI summary
A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.