Dual Gate Semiconductor Device Work Function Control
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Solution Overview
Problem
Current methods for manufacturing semiconductor devices with dual gates face challenges in independently controlling the work functions of n-type and p-type transistors, leading to degradation of high-k dielectric characteristics during the gate etching process, which affects the threshold voltages of metal-oxide semiconductor (MOS) transistors.
Innovation Solution
A method involving the formation of dual gate semiconductor devices with different conductive layers and capping layers on a semiconductor substrate, where the first metallic conductive layer is thin and includes materials like TiN, and the second metallic conductive layer is thicker and formed of materials like TaN, with ion implantation of n-type impurities to adjust work functions, and the use of capping layers to prevent impurity diffusion, allowing for independent control of work functions and maintaining high-k dielectric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a mask process is added to form gates of different materials for independent work function control, then the work function control is improved, but the manufacturing complexity increases
Solution Approach 1:
The gate electrode is segmented into two distinct metallic conductive layers (first and second metallic conductive layers) with different materials and thicknesses. This segmentation allows each layer to contribute differently to the work function, enabling independent control of threshold voltages for NMOS and PMOS transistors without requiring additional mask processes.
Solution Approach 2:
The first metallic conductive layer is selectively formed only in the first region (NMOS region) while the second metallic conductive layer is formed in both first and second regions. This local quality differentiation allows the gate structure to have different electrical characteristics in different regions, achieving independent work function control through spatially varying material composition rather than additional masking steps.
2Manufacturing precision
If gate etching is performed to form separate gates, then the gate structure is improved, but the high-k dielectric layer is damaged
Solution Approach 1:
The gate dielectric layer and metallic conductive layers are formed with predetermined thicknesses and material compositions before the patterning process. The first metallic conductive layer is formed with a thickness of 1-5 nm and the second metallic conductive layer with 5-50 nm, creating a structure that can be patterned without damaging the underlying high-k dielectric layer. This preliminary structuring ensures that subsequent etching processes can define the gate structure while preserving the integrity of the gate dielectric layer.
3Length of moving object
If the gate dielectric layer is made thinner for size reduction, then the device size is reduced, but the high-k dielectric characteristic is degraded
Solution Approach 1:
The gate electrode is constructed as a composite structure using two different metallic conductive layers with distinct materials and properties. The first metallic conductive layer (1-5 nm thick) and second metallic conductive layer (5-50 nm thick) are combined to create a gate structure that provides both the electrical characteristics needed for threshold voltage control and the mechanical stability required to protect the high-k dielectric layer during manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of work functions for NMOS and PMOS transistors, reducing the threshold voltage of NMOS transistors and increasing that of PMOS transistors, while maintaining the integrity of the high-k dielectric layer, thus enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
performing ion plantation of a first material into the first metallic conductive layer of the first region
Implementation Method 2
forming a first capping layer on the gate dielectric layer in the first region... to prevent impurity diffusion
Data Source
AI summary
The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region. The first and second regions of the semiconductor substrate having different work functions because the gate electrodes of the first and second regions have different thicknesses and at least one of the first and second gate electrodes include impurities.