Dual-Gate Transistor Shift Register for Low Power Driving
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Solution Overview
Problem
Conventional shift registers in gate driving circuits of liquid crystal display panels face challenges in achieving high resolution while minimizing power consumption, as increasing the size of single-gate transistors to enhance conduction current leads to excessive power consumption.
Innovation Solution
The use of a dual-gate transistor in the pull-up circuit of the shift register, with a control circuit generating a control signal and a pull-down circuit to manage the potential, allows for a larger conduction current with a smaller transistor size, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of the single-gate transistor is increased to enhance conduction current for high resolution, then the driving capability is improved, but the power consumption becomes excessive
Solution Approach 1:
The patent changes the fundamental parameter of the transistor from single-gate to dual-gate configuration. This structural parameter change enables the transistor to achieve higher conduction current with smaller size by utilizing the unique electrical characteristics of dual-gate transistors, where the second gate can modulate the channel conductivity independently, thus improving driving capability without proportionally increasing power consumption
Solution Approach 2:
The invention adds another dimension of control by introducing a second gate to the transistor structure. This additional control dimension allows for independent optimization of conduction current and power consumption through separate gate control, enabling the transistor to operate at optimal points that balance driving capability and energy efficiency
Data Source
AI summary
A shift register includes a control circuit, a pull-up circuit and a pull-down circuit. The control circuit generates a control signal according to a start pulse signal during being enabled. The pull-up circuit produces a gate pulse signal according to a clock signal during being enabled by the control signal. The pull-up circuit includes a dual-gate transistor. A first gate of the dual-gate transistor is electrically coupled to the control signal, a second gate of the dual-gate transistor is electrically coupled to a predetermined voltage, the source/drain of the dual-gate transistor serves as an output terminal for the gate pulse signal, and the drain/source of the dual-gate transistor is electrically coupled to the clock signal. The pull-down circuit pulls a potential at the first gate and another potential at the output terminal down to a power supply potential during the pull-up circuit is disabled.