Dual-Gate Tunnel FET Structure for Unipolar Logic Switching
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Solution Overview
Problem
Tunnel field-effect transistors (TFETs) face limitations in logic applications due to their ambipolar nature and structural asymmetry, which leads to power dissipation issues and challenges in implementing distinct 'ON' and 'OFF' states, particularly in pass-gate logic used in SRAM.
Innovation Solution
A tunnel field-effect transistor with a p-i-n structure and dual gate electrodes, where the source-channel and drain-channel gate electrodes are independently controlled by insulators, allowing for tailored bias application to control tunnelling currents and implement unipolar operation, enabling the use in XNOR logic gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If TFETs are used for logic applications, then power dissipation is reduced due to sub-kT/q sub-threshold slope, but the ambipolar nature and structural asymmetry prevent distinct ON and OFF states
Solution Approach 1:
The device is segmented into two separate gates: a first gate electrode controlling the source-channel interface and a second gate electrode controlling the drain-channel interface. This segmentation allows independent control of carrier injection and extraction, enabling unipolar operation while maintaining low power dissipation through band-to-band tunneling mechanisms.
Solution Approach 2:
The invention transitions from a conventional single-gate TFET to a dual-gate configuration where gates are positioned at different interfaces (source-channel and drain-channel). This dimensional change in gate control architecture enables distinct ON and OFF states by independently managing carrier flow at each interface, resolving the ambipolar behavior issue.
2Use of energy by moving object
If TFETs are used as CMOS successors, then lower operating voltage is achieved, but structural asymmetry hinders implementation in certain logic applications like pass-gate logic
Solution Approach 1:
The dual-gate TFET structure provides multi-functionality by enabling both low-voltage operation through band-to-band tunneling and versatile logic application implementation through independent gate control. The separate control of source-channel and drain-channel interfaces allows the device to function in various logic configurations including pass-gate logic, enhancing adaptability while maintaining low operating voltage.
3Loss of energy
If gate leakage current is reduced to lower power consumption, then thicker gate dielectric is needed, but this increases device area and may affect switching speed
Solution Approach 1:
The gate structure is segmented into two separate gate electrodes with respective gate dielectrics at different interfaces. This allows each gate dielectric to be independently optimized: the first gate dielectric can be thicker to reduce leakage from the source side, while the second gate dielectric can be thinner to maintain effective control at the drain side, avoiding the need for uniformly thick dielectric across the entire device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power dissipation and enhances switching speeds by allowing distinct 'ON' and 'OFF' states, facilitating the use of TFETs in diverse logic applications, including XNOR logic gates, with improved tunnelling current control and reduced leakage current.
Implementation Method 1
tunnel field-effect transistor with independently controllable source-channel and drain-channel gate electrodes
Implementation Method 2
at least an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and at least the interface between the source region and the channel region
Data Source
AI summary
A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region.