Dual-Gate Thin Film Transistor Channel Length Control
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Solution Overview
Problem
The existing manufacturing method for top-gate electrode thin film transistors results in a short channel effect, causing a negative drift in threshold voltage and affecting the stability and display quality of display devices due to the significant shortening of the channel length during the etching process.
Innovation Solution
A method involving the formation of a thin film transistor with a first gate electrode and a second gate electrode of different thicknesses, where the first gate electrode is used as a mask to define the channel region, ensuring the channel length is maintained and preventing excessive etching bias, thereby stabilizing the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional top-gate electrode thin film transistor manufacturing method is used, then the manufacturing process is simple, but the channel length is significantly shortened causing short channel effect
Solution Approach 1:
The gate electrode is divided into two separate layers: a first gate electrode layer and a second gate electrode layer. This segmentation allows independent control of each layer's thickness and material composition, enabling precise channel length definition while maintaining manufacturing simplicity. The first gate electrode layer serves as the primary channel length definition mask, while the second layer provides additional functionality without interfering with channel length control.
Solution Approach 2:
The first gate electrode layer is formed before the second gate electrode layer, and the first layer is used to define the channel length region in advance. This preliminary action establishes the critical channel length dimension before subsequent processing steps, preventing channel length shortening that would occur if only a single gate layer were used.
2Productivity
If the channel length is significantly shortened during etching, then the etching process is efficient, but the threshold voltage drifts negatively affecting stability
Solution Approach 1:
The first gate electrode layer acts as an intermediary element between the etching process and the active layer. It serves as a protective mask during etching, defining the channel length region and preventing excessive etching that would shorten the channel. This intermediary layer allows efficient etching while maintaining the intended channel length, thereby preventing threshold voltage drift.
3Device complexity
If a single gate electrode structure is used, then the device structure is simple, but the short channel effect affects display quality
Solution Approach 1:
The gate electrode is segmented into two distinct layers with different materials and thicknesses. The first gate electrode layer (e.g., ITO with 150-1500 Å thickness) defines the channel length, while the second gate electrode layer (e.g., metal material) provides additional electrical functionality. This segmentation enables precise channel length control without significantly increasing overall device complexity.
Solution Approach 2:
Different regions of the gate structure have different properties: the first gate electrode layer has optimized thickness and material for channel length definition, while the second gate electrode layer has properties optimized for electrical performance. This local quality differentiation allows precise channel length control in the first layer without compromising overall device performance.
Data Source
AI summary
A thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The thin film transistor is formed on a substrate and includes: an active layer on the substrate, the active layer including a source region, a drain region, and a channel region between the source region and the drain region; a first gate electrode on a side of the active layer away from the substrate; and a second gate electrode on a side of the first gate electrode away from the substrate, wherein a thickness of the first gate electrode is smaller than a thickness of the second gate electrode.