Dual-Gate Thin Film Transistor With Composite Channel Layer
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Solution Overview
Problem
Large size display devices require a large number of thin film transistors (TFTs) which increases the complexity and weight of the display panel, and existing TFT designs do not efficiently address the need for improved response speed and reduced weight.
Innovation Solution
The TFT substrate design incorporates a channel layer with a first portion made of oxide or polycrystalline silicon semiconductor material and a second portion made of conductive or transparent conductive material, where the second portion has higher conductivity and electron mobility, allowing for improved current passage and reduced distance between electrodes, enhancing response speed and reducing weight.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of TFTs is increased to support large size display devices, then the display resolution and coverage are improved, but the weight and complexity of the display panel increase
Solution Approach 1:
The patent changes the material parameters of the channel layer by introducing a second portion made of conductive material with higher conductivity and electron mobility than the first portion. This parameter change allows for reduced electrode distances and improved response speed without increasing the overall TFT area, thereby maintaining display panel area while reducing the need for additional TFTs to achieve the same performance level
Solution Approach 2:
The channel layer is constructed as a composite structure with two different materials: the first portion made of oxide or polycrystalline silicon semiconductor material and the second portion made of conductive or transparent conductive material. This composite channel layer achieves superior electrical properties that allow for more efficient current passage, reducing the number of TFTs needed and thereby reducing overall display panel weight
2Ease of manufacture
If conventional channel layer materials are used, then the manufacturing process is simple, but the response speed of TFTs is insufficient
Solution Approach 1:
The patent modifies the electrical parameters of the channel layer by incorporating a second portion with higher conductivity and electron mobility. This parameter enhancement directly improves the response speed of the TFT by enabling faster charge carrier transport, while the manufacturing process remains compatible with existing semiconductor fabrication techniques
Solution Approach 2:
The composite channel layer structure combines materials with different electrical properties to achieve optimal performance. The second portion made of conductive or transparent conductive material provides high electron mobility for fast response, while the first portion provides semiconductor characteristics for proper TFT operation, achieving both fast response speed and ease of manufacture
3Speed
If the distance between source and drain electrodes is reduced to improve response speed, then the response speed increases, but the conductivity requirements of the channel layer material increase
Solution Approach 1:
The patent directly addresses the conductivity requirement by introducing a second portion in the channel layer made of conductive or transparent conductive material with significantly higher conductivity than conventional semiconductor materials. This parameter change enables the channel layer to maintain high conductivity even when the electrode distance is reduced, ensuring reliable current passage while achieving fast response speed
Solution Approach 2:
The composite channel layer structure provides a solution where the second portion with high conductivity ensures reliable current flow through the reduced electrode gap, while the overall structure maintains proper TFT functionality. This composite approach simultaneously achieves reduced electrode distance for fast response and sufficient conductivity for reliable operation
Data Source
AI summary
A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region.