Dual Gate TFT Mask Alignment and Doping
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Solution Overview
Problem
The conventional manufacturing process of polysilicon thin film transistors (TFTs) for liquid crystal displays (LCDs) is complex and prone to misalignment of mask patterns, leading to varying electrical performances and reduced reliability due to the need for multiple mask processes and doping steps.
Innovation Solution
A method that reduces the number of masks required by using a dual gate TFT structure and ion doping processes to form symmetrical lightly doped regions, allowing for the same mask process to be applied across different TFTs, thereby simplifying the manufacturing process and improving alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes and doping steps are used to form LDD regions with different dopant concentrations, then the electrical performance can be optimized, but the manufacturing process becomes more complex and alignment difficulty increases
Solution Approach 1:
The patent combines multiple doping steps into a single ion implantation process by using a dual-layer mask structure. The first mask layer defines the LDD region boundaries while the second mask layer controls the source/drain region doping, allowing simultaneous formation of different doped regions in one processing step, thereby reducing process complexity while maintaining electrical performance
Solution Approach 2:
The mask structure is segmented into two functional layers: a first mask layer for defining LDD regions and a second mask layer for defining source/drain regions. This segmentation allows each layer to perform its specific function independently, enabling precise control of dopant distribution without requiring multiple sequential mask processes
2Manufacturing precision
If multiple mask processes are used to form source region, drain region and LDD region, then different dopant concentrations can be achieved, but mask alignment difficulty increases
Solution Approach 1:
The patent merges the alignment requirements of multiple mask processes into a single alignment operation. By forming both the LDD region mask and source/drain region mask in one step using vertically stacked mask layers, the alignment error between different mask patterns is eliminated, achieving precise dopant concentration control without compromising mask alignment precision
Solution Approach 2:
The patent transitions from planar mask alignment in two dimensions to vertical stacking in three dimensions. Instead of aligning multiple masks laterally on the same plane, the mask patterns are stacked vertically, converting the alignment problem from a 2D lateral alignment issue to a 3D vertical positioning issue, which is easier to control with standard lithography tools
3Ease of manufacture
If conventional doping processes are used, then source region and drain region can be formed, but the process takes more than two doping steps increasing manufacturing time
Solution Approach 1:
The patent combines multiple doping steps into a single ion implantation process. By using the vertically stacked dual-layer mask structure, the patent achieves simultaneous doping of LDD regions and source/drain regions in one ion implantation step, reducing the manufacturing cycle time while maintaining the capability to form all required doped regions with appropriate concentrations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and electrical performance of TFTs by reducing manufacturing complexity, increasing processing yield, and lowering costs through improved mask alignment and simplified processes.
Implementation Method 1
a first type ion doping process is performed on the first source/drain region and the second source/drain region using the first mask pattern, the first gate pattern, the second mask pattern and the second gate pattern as masks so that the first source/drain region and the second source/drain region have a first conductive state
Implementation Method 2
an etching process is performed on the first mask pattern and the second mask pattern to remove a portion of exterior walls of the first mask pattern and the second mask pattern so that a portion of the first gate pattern and a portion of the second gate pattern are exposed
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost.