Dual-Gate TFT Structure for Reducing OLED Image Retention
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Solution Overview
Problem
Existing OLED display devices suffer from image retention due to hysteresis characteristics in thin film transistors (TFTs), which affect the display's ability to change from a black to a white picture, and require inefficient manufacturing processes with multiple masks for forming complex transistor structures.
Innovation Solution
A dual-gate driving TFT structure with a storage capacitor electrode made of impurity-doped semiconductor, formed on the same layer as the semiconductor area, reduces hysteresis and allows for self-aligned doping, thereby minimizing image retention and the number of masks required in manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TFT structure is used, then device complexity is reduced, but hysteresis characteristics cause image retention
Solution Approach 1:
The gate electrode is divided into two separate gates (first gate electrode and second gate electrode) positioned at different locations relative to the channel. This segmentation allows independent control of the channel from both sides, effectively reducing hysteresis characteristics and improving image retention without excessive complexity
Solution Approach 2:
The invention adds a spatial dimension by positioning gate electrodes at different heights (first gate at lower level, second gate at upper level) and different horizontal positions (one at each side of the channel). This three-dimensional gate arrangement reduces hysteresis while maintaining manageable device complexity
2Manufacturing precision
If multiple masks are used for patterning, then manufacturing precision is improved, but productivity is reduced
Solution Approach 1:
The first gate electrode and second gate electrode are formed simultaneously in the same patterning step using a single mask. This merging of formation steps maintains the precise positioning of both gates while reducing the total number of masks and processing steps, thereby improving manufacturing efficiency
Solution Approach 2:
The gate electrodes are positioned in advance during the semiconductor layer formation stage, allowing subsequent doping and processing steps to proceed without additional masking operations. This preliminary positioning maintains precision while streamlining the overall manufacturing process
3Area of stationary object
If storage capacitor electrode overlaps top gate electrode, then area is reduced, but hysteresis increases
Solution Approach 1:
The storage capacitor electrode is positioned in a specific location (outside the overlap area with the top gate electrode) where it can form the necessary capacitance without interfering with the gate-controlled channel region. This localized positioning maintains small pixel area while avoiding hysteresis degradation
Solution Approach 2:
The bottom gate electrode serves as an intermediary structure that the storage capacitor electrode can overlap with, providing the necessary capacitive function without directly overlapping the top gate electrode. This intermediary arrangement preserves both area efficiency and hysteresis characteristics
Data Source
AI summary
A circuit includes a first thin film transistor configured to supply electric current to an organic light-emitting film, and a storage capacitor. The first thin film transistor includes a bottom gate electrode, a channel provided on a layer upper than the bottom gate electrode to overlap with the bottom gate electrode, and a top gate electrode. The storage capacitor includes a storage capacitor electrode made of an impurity semiconductor, the storage capacitor electrode being provided outside an overlap area with the top gate electrode on the same layer as the channel to overlap with the bottom gate electrode with the first gate insulating layer interposed.