Dual Conformal Gate GAA Transistor for Threshold Voltage Tuning
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Solution Overview
Problem
Current GAA transistor architectures face challenges in finely adjusting threshold voltage and achieving a wide range of accessible threshold voltages, limiting their versatility and performance, especially at technological nodes below 3 nm.
Innovation Solution
A microelectronic device with a dual gate architecture featuring two independently polarizable grids surrounding the channels, along with a process that selectively forms and structures semiconductor material layers to enhance control over threshold voltage, utilizing a stack of alternating materials and selective engraving to create internal spacers and grids, allowing for the introduction of 2D materials like MX2 dichalcogenides at a late stage to preserve their integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate is used in GAA transistor architecture, then the device structure is simpler, but the threshold voltage control is limited
Solution Approach 1:
The single gate structure is segmented into two separate gates (first gate and second gate) that can be independently controlled. Each gate surrounds different portions of the channel, allowing independent biasing and continuous adjustment of the threshold voltage across a wide range, thereby resolving the contradiction between structural simplicity and control versatility.
Solution Approach 2:
The invention transitions from a single-plane gate configuration to a multi-dimensional gate arrangement where the first and second gates are positioned at different heights and orientations around the channel. This spatial dimensionality enhancement enables independent control of threshold voltage without significantly increasing overall device complexity.
2Productivity
If semiconductor materials are processed early in manufacturing, then the process sequence is simpler, but the material integrity is compromised
Solution Approach 1:
The semiconductor material layers are prepared and positioned in advance as part of the alternating stack structure, but their final processing and formation into functional channels is delayed until after the gate structures are completed. This preliminary positioning without early processing preserves material integrity while maintaining an efficient overall process sequence.
Solution Approach 2:
Instead of the conventional approach where semiconductor material is processed first and then gates are added, the invention inverts the sequence by completing gate structure formation first and then processing the semiconductor material layers. This reversed sequence protects the semiconductor material from degradation while maintaining manufacturing efficiency.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
The invention relates to a microelectronic device comprising a transistor (T1, T2) having: • at least two channels (41a, 41b, 41c) stacked along a principal direction (z), • a first gate (G1) partially surrounding one of the channels (41a, 41b, 41c), • a second gate (G2) partially surrounding said channel (41), • a source (42) and a drain (43) on either side of the channels (41a, 41b, 41c), and source and drain contacts (60S, 60, 60D) connected respectively to the source (42) and the drain (43), • a dielectric layer (70, 71, 72) of the gate separating each channel (41) from the surrounding gates (G1, G2). The first and second gates (G1, G2) are insulated from each other so that they can be independently biased. The invention also relates to a method for making such a device.