Dual Gate Thyristor Memory Cell Cathode Segmentation
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Solution Overview
Problem
The semiconductor device industry faces challenges in improving the operation of electronic devices due to issues with thyristor random access memory (TRAM) cells, particularly with common cathode structures that can lead to unselected cells being turned on by reading another cell, causing read disturb and data retention problems.
Innovation Solution
The implementation of a dual gate thyristor memory cell with a fixed cathode and specific pulse schemes for writing data, including intermediate voltage levels and adjusted access pulses, to prevent unselected cells from turning on during read operations, thereby reducing read disturb and enhancing data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common cathode structure is used in TRAM cells, then device complexity is reduced and manufacturing is simplified, but read disturb occurs where unselected cells are turned on during read operations
Solution Approach 1:
The cathode is segmented into individual cathodes for each memory cell rather than using a common cathode. This segmentation isolates each cell electrically, preventing current from flowing through unselected cells during read operations, thereby eliminating read disturb while maintaining manufacturing feasibility through systematic fabrication processes
Solution Approach 2:
Each memory cell is given its own dedicated cathode with specific electrical characteristics optimized for that cell's operation. This local quality approach ensures that voltage changes in one cell do not affect neighboring cells, preventing read disturb while allowing each cell to be independently controlled and retained reliably
2Productivity
If standard read operations are performed on TRAM cells, then data retrieval is achieved, but unselected cells may turn on causing read disturb
Solution Approach 1:
By segmenting the cathode structure into individual cathodes for each cell, the patent enables selective activation of only the target cell during read operations. The isolated cathode structure prevents current leakage to adjacent cells, allowing fast data retrieval without causing read disturb to unselected cells
Solution Approach 2:
The individually controlled cathodes act as intermediaries between the select lines and the memory cell transistors. By controlling each cathode independently, the system can precisely activate only the desired cell during read operations, preventing harmful current flow to unselected cells while maintaining efficient data retrieval
Data Source
AI summary
Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.