Dual Gate Transistor with Auxiliary Electrode for Compact Display Drivers
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Solution Overview
Problem
Current display technologies face challenges in reducing the area occupied by driving circuits, particularly transistors, which limits the achievement of high resolution and narrow bezel designs in display devices.
Innovation Solution
The implementation of a dual gate transistor structure, where two transistors are connected in series with an auxiliary electrode on a different layer, and multiple gate transistors with gate electrodes connected through contact holes in an insulating layer, reduces the physical area occupied by the transistors and enhances stability, allowing for a more compact and efficient display panel design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional transistor structures are used in display driving circuits, then the circuit functionality is achieved, but the area occupied by the driving circuits is large
Solution Approach 1:
The transistor channel is divided into two separate channel layers (first channel layer and second channel layer) stacked vertically, with each layer controlled by its own gate electrode. This segmentation allows the transistor to be split into functional sections that can be independently optimized, reducing the horizontal area while maintaining control effectiveness.
Solution Approach 2:
The invention transitions from a planar transistor structure to a three-dimensional stacked structure by arranging channel layers vertically in the thickness direction. This dimensional change enables the transistor to achieve equivalent control with reduced footprint area, as the gate electrodes control the channel through vertical stacking rather than horizontal extension.
2Area of stationary object
If the area occupied by transistors is reduced to achieve high resolution and narrow bezel, then display quality improves, but leakage current increases and circuit stability deteriorates
Solution Approach 1:
The channel is segmented into two independent channel layers, each controlled by its own gate electrode. This segmentation allows independent optimization of each channel layer's thickness and material properties to minimize leakage current while maintaining low area occupation.
Solution Approach 2:
The invention uses composite channel structures where different channel layers can be made from different materials (e.g., amorphous silicon, crystalline silicon, oxide semiconductors) to optimize performance. This composite approach enables reduction of leakage current by selecting materials with appropriate electrical properties for each layer while maintaining compact area.
Data Source
AI summary
Provided is a display panel to which a dual gate transistor is applied. The display panel includes a substrate including a pixel area and a non-pixel area and a dual gate transistor disposed on the non-pixel area. The dual gate transistor includes first and second transistors which are connected in series and an auxiliary electrode which connects two gate electrodes of the first and second transistors. The auxiliary electrode is on a layer which is different from the gate electrode. Therefore, an area in which the dual gate transistor is formed is reduced and stability of the driving circuit is secured.