Dual-Gate Transistor Channel Distribution for On-Resistance Reduction
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Solution Overview
Problem
Conventional transistors face challenges in increasing drain current as they shrink, leading to higher on-resistance and reduced RF performance due to limited channel distribution away from the gate structure.
Innovation Solution
The method involves forming a transistor with two gate structures on either side of an active layer, sharing a source-drain region, and using a conductive material to create plug structures aligned in the same direction, facilitating improved current distribution across the active layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the transistor size is decreased to increase device density, then the device integration degree is improved, but the drain current increases more difficultly leading to higher on-resistance
Solution Approach 1:
The gate structure is divided into two separate gates positioned on opposite sides of the active layer. This segmentation allows the channel to be distributed across both gates, effectively increasing the total channel width and drain current capability even as the overall transistor footprint decreases.
Solution Approach 2:
The transistor architecture transitions from a planar single-gate structure to a three-dimensional dual-gate configuration where gates are positioned on opposite sides of the active layer. This dimensional change enables better current distribution and reduced on-resistance without increasing the planar area.
2Area of stationary object
If the transistor size is decreased to increase device density, then the device integration degree is improved, but the RF performance deteriorates due to limited channel distribution
Solution Approach 1:
The gate structure is divided into two separate gates positioned on opposite sides of the active layer. This segmentation allows the channel to be distributed across both gates, effectively increasing the total channel width and drain current capability even as the overall transistor footprint decreases.
Solution Approach 2:
The transistor architecture transitions from a planar single-gate structure to a three-dimensional dual-gate configuration where gates are positioned on opposite sides of the active layer. This dimensional change enables better current distribution and reduced on-resistance without increasing the planar area.
3Device complexity
If a single gate structure is used to simplify device structure, then the manufacturing process is easier, but the drain current is limited and on-resistance is high
Solution Approach 1:
The gate structure is divided into two separate gates positioned on opposite sides of the active layer. This segmentation allows the channel to be distributed across both gates, effectively increasing the total channel width and drain current capability even as the overall transistor footprint decreases.
Data Source
AI summary
The present disclosure provides a method for forming a transistor, including: forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer; forming a second gate structure on the active layer; forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure; and forming a first interlayer dielectric layer covering the base structure and the second gate structure. The method also includes: forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure; and forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer.