Dual Gate Transistor Sense Amplifier for DRAM Area Reduction

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Solution Overview

Problem

Conventional sense amplifiers in DRAM circuits consume significant area and increase fabrication costs due to their complex structure and high overhead, necessitating a reduction in area consumption while maintaining effective voltage sensing capabilities.

Innovation Solution

A simplified circuit for sensing voltage differences on dual signal lines, featuring a pair of cross-coupled inverters with dual gate transistors and a decode transistor that establishes a short circuit between the signal lines to generate a voltage difference, eliminating the need for dedicated precharge and decode transistors, and utilizing a semiconductor-on-insulator substrate for reduced area consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional sense amplifier circuit with dedicated precharge transistors and decode transistors is used, then the voltage sensing capability is reliable, but the area consumption and fabrication cost increase significantly

Engineering Contradiction:
Improvevoltage sensing capabilityVSAvoidarea consumption
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the functions of precharge transistors and decode transistors into the dual gate transistors (T1, T2, T3, T4) that form the cross-coupled inverter structure. The first gate controls decoding operation while the second gate controls precharge/equalization, eliminating the need for separate dedicated transistors and reducing overall circuit area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The dual gate transistors serve multiple functions simultaneously: they act as both decode transistors (controlled by first gate) and precharge/equalization transistors (controlled by second gate). This multi-functionality reduces the total transistor count from 10 in conventional circuits to just 4 transistors in the sense amplifier.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a conventional sense amplifier with ten transistors is implemented, then effective voltage sensing is achieved, but the device complexity and fabrication cost increase

Engineering Contradiction:
Improvevoltage sensing effectivenessVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple transistor functions into a single dual gate transistor structure. The cross-coupled inverter pair (T1-T4) with dual gates integrates the roles of precharge transistors, decode transistors, and sensing transistors, reducing device complexity from 10 separate transistors to 4 multi-functional transistors.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each dual gate transistor is designed to perform multiple operations: the first gate controls the decode function while the second gate controls the precharge and equalization functions. This universal design simplifies the overall circuit architecture while maintaining all necessary sensing capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If dedicated precharge transistors are used to precharge bit lines to VH/2, then the bit line equilibration is accurate, but the area consumption increases

Engineering Contradiction:
Improvebit line equilibration accuracyVSAvoidtransistor area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The dual gate transistors (T1, T2) serve as both precharge transistors (when second gate is controlled) and decode transistors (when first gate is controlled). This eliminates the need for separate dedicated precharge transistors while maintaining the ability to precharge bit lines to the equilibrium voltage VH/2.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The precharge function is merged into the main inverter structure through the dual gate transistors. The same transistors that form the sensing amplifiers also perform the precharge operation, reducing the total transistor count from 10 to 4 while preserving equilibration accuracy.

Inventive Principle:
Principle #5Merging (Combining)

4Ease of manufacture

If conventional bulk silicon CMOS technology is used for sense amplifier fabrication, then the circuit is well-established, but the area consumption and fabrication cost are high

Engineering Contradiction:
Improvefabrication process maturityVSAvoidsense amplifier area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent transitions from conventional bulk silicon CMOS to semiconductor-on-insulator (SOI) technology. This parameter change in the substrate type enables the implementation of dual gate transistors with improved performance and reduced area, while the simplified circuit structure (4 transistors vs. 10) further reduces the overall area requirement.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses semiconductor-on-insulator composite structure, combining a semiconductor layer with an insulator layer to enable dual gate transistor operation. This composite material approach allows for reduced area consumption while maintaining fabrication compatibility with established processes.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS9390771B2Circuit and method for sensing a difference in voltage on a pair of dual signal lines, in particular through equalize transistor
Publication Date: 2016.07.12 SOITEC SA
  • US9390771B2 patent drawing
  • US9390771B2 patent drawing
  • US9390771B2 patent drawing

AI summary

A circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising:a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals,a decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.