Dual-Gate Transistor with Shared Oxide Layer
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Solution Overview
Problem
Existing semiconductor devices face challenges with increased parasitic capacitance due to the number of oxide semiconductor layers, which affects transistor driving and requires a novel approach to reduce the number of these layers while minimizing parasitic capacitance.
Innovation Solution
The semiconductor device design includes a configuration where one oxide semiconductor layer has both a first and second channel formation region, with specific conductive layers having openings that overlap, reducing the number of oxide semiconductor layers and minimizing parasitic capacitance by allowing for a higher degree of freedom in the shape of the conductive layers, thereby decreasing the probability of disconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If parallel connection of first transistor and second transistor is implemented, then transistor driving capability is improved, but number of oxide semiconductor layers increases and parasitic capacitance increases
Solution Approach 1:
The patent merges the channel formation regions of two transistors into a single oxide semiconductor layer. The first and second channel formation regions are formed in the same oxide semiconductor layer rather than using separate layers, thereby reducing the total number of oxide semiconductor layers while maintaining parallel transistor functionality and reducing parasitic capacitance.
Solution Approach 2:
The single oxide semiconductor layer serves multiple functions by forming both the first channel formation region and the second channel formation region. This multi-functional use of the oxide semiconductor layer allows two transistors to operate in parallel without requiring separate oxide semiconductor layers for each transistor.
2Power
If multiple oxide semiconductor layers are used for parallel transistors, then transistor driving capability is improved, but parasitic capacitance increases affecting transistor driving
Solution Approach 1:
The patent combines the channel formation regions of two transistors into a single oxide semiconductor layer, thereby reducing parasitic capacitance between stacked oxide semiconductor layers while maintaining the parallel transistor configuration for improved driving capability.
3Ease of manufacture
If conductive layers are made with standard shapes, then manufacturing is simpler, but degree of freedom in shape is limited and disconnection probability increases
Solution Approach 1:
The patent introduces openings in the conductive layers, allowing the conductive layer shapes to be dynamically adjusted and optimized. The openings enable better stress distribution and thermal management, increasing the degree of freedom in shape design while reducing disconnection probability through improved structural flexibility.
Data Source
AI summary
Two dual-gate transistors, which are electrically connected in parallel and provided in a compact design, are disclosed.