Dual-Gate Trench TFT Structure for Short-Channel Control
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Solution Overview
Problem
There is a need for improved thin film transistors (TFTs) that offer enhanced performance and density, particularly in applications like embedded dynamic random access memory (eDRAM), where existing TFTs face challenges in short channel control, contact resistance, and parasitic gate to source/drain capacitance.
Innovation Solution
The development of dual gate trench shaped thin film transistors with a non-planar semiconductor layer, featuring a first gate electrode structure adjacent to a first gate dielectric layer and a second gate electrode structure within a trench, providing dual gate control and improved short channel control while maintaining low contact resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar TFT structure is used, then manufacturing is simple, but gate control is poor and device density is low
Solution Approach 1:
The patent transitions from a planar two-dimensional gate structure to a three-dimensional trench-shaped gate structure. The gate electrode is formed within a trench that extends into the semiconductor layer, providing gate control from multiple directions (top and sidewalls). This dimensional change enables superior electrostatic control over the channel while maintaining compatibility with standard TFT fabrication processes.
Solution Approach 2:
The gate structure is segmented into multiple components: a bottom gate electrode at the trench base and sidewall gate electrodes forming the trench walls. This segmentation allows independent optimization of gate control in different regions, with the bottom gate providing primary control and sidewall gates enhancing short-channel effects control.
2Productivity
If channel length is reduced to increase device density, then productivity increases, but short channel control deteriorates
Solution Approach 1:
By forming the gate within a trench that penetrates into the semiconductor layer, the patent achieves three-dimensional gate control. This allows the gate to control the channel from the top and sidewalls simultaneously, providing excellent electrostatic control even when the lateral channel length is reduced to increase device density.
Solution Approach 2:
The gate electrode is nested within the trench structure that is formed within the semiconductor layer. This nested configuration allows the gate to be positioned deep within the device structure, maximizing its control over the channel region while minimizing the lateral footprint and enabling higher device density.
3Reliability
If gate dielectric thickness is reduced to improve control, then gate control improves, but contact resistance and parasitic capacitance increase
Solution Approach 1:
The trench gate structure provides gate control in three dimensions (top and sidewalls), enabling effective electrostatic control with a relatively thicker gate dielectric. This eliminates the need to reduce gate dielectric thickness to the extent that parasitic effects dominate, as the multi-directional gate control compensates for the increased dielectric thickness.
Solution Approach 2:
The gate dielectric is positioned specifically within the trench region where it is needed for gate control, rather than being a continuous layer across the entire device. This localized positioning reduces the total gate dielectric area, thereby reducing parasitic capacitance while maintaining effective gate control where the channel is formed.
Data Source
AI summary
Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.