Dual Gate Structure Layout for Ultra-Low-Vt NFET and PFET
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve ultra-low threshold voltages in FETs without increasing gate resistance, particularly in multi-threshold voltage devices, while maintaining cost-effectiveness and time efficiency.
Innovation Solution
The formation of FETs with different gate structure configurations, including Al-based n-type and Al-free p-type work function metal layers, allows for ultra-low threshold voltages in both NFETs and PFETs on the same substrate, reducing gate resistance and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate structures are used to achieve ultra-low threshold voltages, then threshold voltage is reduced, but gate resistance increases
Solution Approach 1:
The patent applies different material compositions to different regions of the gate structure. Specifically, it uses Al-based n-type work function metal layers for NFETs and Al-free p-type work function metal layers for PFETs, creating locally optimized gate structures that achieve ultra-low threshold voltages without increasing gate resistance. This local differentiation allows each transistor type to have tailored electrical properties.
Solution Approach 2:
The gate structure employs composite material layers including work function metal layers, barrier layers, and gate fill layers. The combination of Al-based n-type work function metal with barrier layers and gate fill materials creates a composite structure that simultaneously achieves ultra-low threshold voltage and maintains low gate resistance, resolving the contradiction between these two parameters.
2Manufacturing precision
If different gate structure configurations are formed for NFETs and PFETs, then ultra-low threshold voltages are achieved in both, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation processes of NFET and PFET gate structures into a unified manufacturing sequence. Both n-type and p-type work function metal layers are deposited and processed in an integrated manner, allowing different gate configurations to be achieved simultaneously without requiring separate manufacturing lines or significantly increasing process complexity.
Solution Approach 2:
The invention achieves different gate structure configurations by changing material parameters rather than process parameters. By adjusting the composition (Al-based vs Al-free) and electrical properties (n-type vs p-type) of the work function metal layers, the patent creates distinct gate structures for NFETs and PFETs while maintaining a consistent manufacturing approach, thus reducing the perceived complexity.
3Ease of manufacture
If conventional manufacturing methods are used, then manufacturing is simpler, but cost and time efficiency are reduced
Solution Approach 1:
The gate manufacturing process is designed to be multi-functional, simultaneously achieving multiple objectives: forming different work function metal layers, creating barrier layers, depositing gate fill materials, and producing both NFET and PFET structures in a single integrated process sequence. This universality maintains ease of manufacture while dramatically improving cost and time efficiency by eliminating the need for separate processing steps for different transistor types.
Data Source
AI summary
A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.