Dual-Gate Vertical DRAM Transistors for Layout Efficiency
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Solution Overview
Problem
Current DRAM devices face challenges in scaling down due to limitations in gate width, which affect electrostatic capacitance, retention time, and layout efficiency, particularly in dual-gate structures, leading to increased manufacturing costs and inefficiencies.
Innovation Solution
A dual-gate DRAM device is fabricated using a semiconductor substrate with pillar-shaped active patterns, conductive patterns, and epitaxial layers, where bit lines directly contact the active patterns, and gate insulation films are used between word lines and active patterns, allowing for a simpler and more efficient processing method without the need for contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-gate structure is used, then the gate width can be kept simple, but the retention time decreases and threshold voltage fluctuates due to short channel effects
Solution Approach 1:
The patent transitions from a planar single-gate structure to a three-dimensional dual-gate structure where gate electrodes are positioned above and below the channel region. This dimensional change allows the channel to be surrounded by gates on two sides, effectively doubling the gate control and preventing short channel effects even when the channel length is scaled down, thus maintaining retention time while keeping the structure relatively simple.
Solution Approach 2:
The gate control is segmented into two separate gate electrodes positioned at opposite sides of the channel (above and below). This segmentation allows each gate to independently control the channel, providing better electrostatic control and preventing threshold voltage fluctuation while maintaining acceptable retention time without requiring excessively wide gates.
2Reliability
If a dual-gate structure is used, then retention time and threshold voltage stability improve, but layout efficiency decreases and manufacturing complexity increases
Solution Approach 1:
By positioning gate electrodes in the vertical dimension (above and below the channel) rather than only in the planar dimension, the patent achieves dual-gate control without consuming additional lateral space. This vertical stacking allows the transistor to maintain a compact footprint, improving layout efficiency while still providing the stability benefits of dual-gate control.
3Device complexity
If source and drain regions are arranged horizontally, then the transistor structure is simple, but chip size cannot be scaled down further
Solution Approach 1:
The patent reorients the source and drain regions from a horizontal arrangement to a vertical arrangement, with the channel extending in the vertical direction between source and drain. This vertical configuration allows the transistor to occupy less lateral space, enabling further scaling of chip size while maintaining a relatively simple transistor structure that does not require complex three-dimensional stacking.
4Reliability
If impurity concentration in the channel is increased to prevent short channel effects, then retention time is maintained, but leakage current increases
Solution Approach 1:
The gate control is segmented into two separate gates positioned above and below the channel, providing distributed electrostatic control along the channel length. This segmentation allows each gate to independently suppress short channel effects, maintaining retention time without requiring high impurity concentration, thereby avoiding the increase in leakage current that would result from heavy doping.
Data Source
AI summary
A dynamic random access memory (DRAM) device has dual-gate vertical channel transistors. The device is comprised of pillar-shaped active patterns including source regions contacting with a semiconductor substrate, drain regions formed over the drain regions, and channel regions formed between the source and drain regions. The active patterns are disposed in a cell array field. On the active patterns, bit lines are arranged to connect the drain regions along a direction. Between the active patterns, word lines are arranged intersecting the bit lines. Gat insulation films are interposed between the word lines and active patterns.