Dual-Gate Vertical Thin-Film Transistors for Higher On-Current Density
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Solution Overview
Problem
Planar thin film transistors face challenges in scaling due to material property limitations and process control difficulties, while vertical devices suffer from insufficient source/drain-to-gate overlap, impacting device performance.
Innovation Solution
The development of a semiconductor structure featuring vertical field effect transistors with a dual gate configuration, including an inner gate electrode embedded in a dielectric pillar between a bottom and top electrode, and an outer gate electrode formed above an outer gate dielectric, which provides increased channel width and on-current per device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar thin film transistor structures are used, then manufacturing simplicity is maintained, but device performance and scalability are limited due to material property limitations and process control difficulties
Solution Approach 1:
The patent transitions from planar (2D) transistor structures to vertical (3D) transistor structures by standing the channel region vertically. This dimensional change increases the effective channel width per device area and improves source/drain-to-gate overlap while maintaining compatibility with existing low-temperature processing techniques for oxide semiconductors
2Area of moving object
If vertical transistor structures are used, then device performance is improved through increased channel width, but source/drain-to-gate overlap is insufficient impacting device performance
Solution Approach 1:
The patent implements a dual gate configuration where an inner gate electrode is positioned within the channel region and an outer gate electrode surrounds the channel region externally. This nested arrangement ensures that both gates can effectively modulate the channel, providing sufficient source/drain-to-gate overlap and improved device performance while maintaining the benefits of increased channel width
Data Source
AI summary
A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.