Dual Metal Silicide Gate Electrodes for NMOS and PMOS Work Function Tuning
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Solution Overview
Problem
Current semiconductor devices with polysilicon-doped gate electrodes face challenges in achieving high-speed operation for both NMOS and PMOS transistors due to work function mismatches and depletion regions, leading to decreased operation speed.
Innovation Solution
A semiconductor device with dual gate electrodes made of metal silicides, where the gate insulating layer induces a Fermi pinning effect to optimize work functions, with varying silicon concentrations and materials like nickel, cobalt, or tantalum to adjust the work functions of NMOS and PMOS transistors, ensuring they operate at high speed and low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polysilicon doped with n-type impurities is used for gate electrodes, then productivity is improved by simplifying fabrication process, but operation speed of PMOS transistor decreases due to buried channel formation
Solution Approach 1:
The gate electrode is segmented into two distinct parts: a first gate electrode for NMOS transistor and a second gate electrode for PMOS transistor. This segmentation allows each gate to have independently optimized work functions, enabling high-speed operation for both transistor types while maintaining simplified fabrication processes.
Solution Approach 2:
Different materials are used for the first and second gate electrodes to provide locally optimized properties. The first gate electrode uses material with work function close to silicon conduction-band edge for NMOS, while the second gate electrode uses material with work function close to silicon valence-band edge for PMOS, achieving high-speed operation in both regions.
2Speed
If polysilicon doped with n-type or p-type impurities is used for gate electrodes, then work functions are optimized close to silicon conduction-band or valence-band edge energy levels, but depletion region forms in gate electrodes decreasing operation speed
Solution Approach 1:
The gate electrodes are formed using metal silicide composite materials that provide optimized work functions without forming depletion regions. These composite materials combine the advantages of metal and silicon to achieve high-speed operation while avoiding the harmful depletion effect associated with heavily doped polysilicon.
3Ease of manufacture
If a single gate electrode material is used for both NMOS and PMOS transistors, then fabrication process is simplified, but work function optimization for both transistor types cannot be achieved
Solution Approach 1:
The gate electrode structure is segmented into two separate gate electrodes with different materials, allowing independent work function optimization for NMOS and PMOS transistors while maintaining a relatively simplified fabrication process through sequential formation steps.
Solution Approach 2:
Different material parameters (work functions) are selected for the first and second gate electrodes to match the specific requirements of NMOS and PMOS transistors. This parameter optimization enables high-speed operation for both transistor types by aligning gate work functions with appropriate silicon band edges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual gate electrode structure optimizes the work functions of NMOS and PMOS transistors, enabling them to operate at high speed with improved leakage current characteristics and threshold voltages, thus addressing the limitations of existing technologies.
Implementation Method 1
A gate insulating layer is interposed between the substrate and the first gate electrode, and between the substrate and the second gate electrode. The gate insulating layer brings about a Fermi pinning effect for increasing or decreasing intrinsic work functions of the first and second metal silicides.
Data Source
AI summary
A semiconductor device having a dual gate electrode and a method of forming the same are provided. The semiconductor device includes a substrate including first and second regions. A first gate electrode formed of a first metal silicide is disposed on the substrate of the first region. A second gate electrode is disposed on the substrate of the second region. The second gate electrode is formed of a second metal silicide including a metal the same as that of the first metal silicide. A gate insulating layer is interposed between the substrate and the first gate electrode, and between the substrate and the second gate electrode. The gate insulating layer brings about a Fermi pinning effect increasing or decreasing intrinsic work functions of the first and second metal silicides. In this case, the first metal silicide is a lower silicon concentration than the second metal silicide so that the Fermi pinning effect provided to the first gate electrode is less effective than that provided to the second gate electrode.