Dual-Gated Non-Volatile Memory Cell for Multi-Bit Threshold Control
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in efficiently storing and retrieving multiple bits of data in a single memory cell, particularly in achieving precise control over charge levels and voltage thresholds for different data states.
Innovation Solution
The proposed solution involves a memory cell design that includes two transistors and a capacitor, where the write transistor and read transistor are configured to store and retrieve data by controlling the charge on the capacitor, allowing for multiple bits of data to be stored and read with precise voltage threshold control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single memory cell stores multiple bits of data, then data density increases, but control precision over charge levels and voltage thresholds deteriorates
Solution Approach 1:
The memory cell is segmented into multiple independent control transistors (first write transistor, second write transistor, read transistor) that can independently control different aspects of data storage and retrieval. This segmentation allows precise control over charge levels for multiple data bits stored in the same cell, resolving the contradiction between increased data density and maintained voltage threshold control precision.
2Speed
If access time is reduced for faster data retrieval, then productivity improves, but reliability of data state maintenance deteriorates
Solution Approach 1:
The memory cell performs preliminary charging of the capacitor during the write operation to establish well-defined voltage thresholds before read operations. This preliminary action ensures that data states are reliably established before rapid access operations, maintaining reliability while enabling fast read speeds through the use of dual-gate transistor control.
3Area of stationary object
If data density is increased by storing multiple bits per cell, then area efficiency improves, but complexity of control mechanisms increases
Solution Approach 1:
The read transistor serves multiple functions: it acts as a selection transistor for reading data and simultaneously as a control element for maintaining data state integrity during read operations. This multi-functionality reduces the need for additional dedicated control components, thereby limiting the increase in device complexity while achieving multiple bits per cell storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables efficient storage and retrieval of multiple bits of data in a single memory cell, improving data density and access times while maintaining high reliability and precision in data states.
Implementation Method 1
a first capacitive element is disposed over an upper surface of the first body region and disposed between the first write wordline and the first read bitline. The first capacitive element is configured to selectively store varying levels of charge corresponding to varying data states on the first body region.
Data Source
AI summary
A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.