Dual-Gated Non-Volatile Memory Cell for Multi-Bit Threshold Sensing
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in efficiently storing and reading multiple data bits due to limitations in voltage threshold management and charge storage, leading to inefficiencies in data state determination.
Innovation Solution
The implementation of a two-transistor memory cell with a capacitor, where write and read transistors are coupled with bias circuitry to set and measure voltage thresholds for different data states, allowing for single-bit or multi-bit storage by controlling charge levels on the capacitor, enabling precise data state determination through varying bias conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional memory structures are used, then device complexity is reduced, but measurement precision and data state determination accuracy deteriorate
Solution Approach 1:
The memory cell is segmented into distinct functional regions: a body region for charge storage, a first capacitive element coupled to the body region, and a second capacitive element coupled to the body region. This segmentation allows independent control and measurement of different charge components, improving data state determination accuracy while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
Capacitive elements are introduced as intermediary components between the body region and the read circuitry. These capacitive elements serve as mediators that couple the stored charge in the body region to the measurement circuit, enabling precise data state determination without directly increasing the complexity of the core memory cell structure.
2Productivity
If voltage threshold management is simplified, then device complexity is reduced, but productivity and storage efficiency deteriorate
Solution Approach 1:
The memory cell employs dynamic voltage threshold management where the read transistor's threshold voltage can be adjusted based on the charge state of the capacitive elements. This dynamic adjustment enables efficient multi-bit storage by creating distinct voltage thresholds for different data states, improving storage efficiency while the automated threshold adjustment mechanisms keep complexity manageable.
Solution Approach 2:
The invention utilizes parameter changes in the capacitive elements' charge levels to encode multiple data states. By varying the charge量 on the first and second capacitive elements, the system can represent single-bit or multi-bit data states, improving storage efficiency. The bias circuitry automatically manages the corresponding voltage threshold changes, maintaining reasonable device complexity.
3Productivity
If charge storage capacity is increased for multi-bit storage, then productivity improves, but reliability and charge management complexity worsen
Solution Approach 1:
The charge storage function is segmented across multiple capacitive elements (first capacitive element and second capacitive element) rather than relying on a single large capacitor. This segmentation distributes the charge storage burden, improving reliability by reducing the impact of defects in any single capacitive element while enabling multi-bit storage capacity.
Solution Approach 2:
The memory cell incorporates feedback mechanisms where the charge state of the capacitive elements influences the operation of the read transistor and write transistor. This feedback ensures reliable charge management by automatically adjusting read/write operations based on the current charge state, maintaining high reliability even with increased charge storage capacity for multi-bit storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient storage and reading of single-bit or multi-bit data states by effectively managing voltage thresholds, improving data state determination accuracy and storage efficiency in semiconductor memory cells.
Implementation Method 1
a first capacitive element disposed over an upper surface of the first body region and disposed between the first write wordline and the first read bitline. The first capacitive element is configured to selectively store varying levels of charge corresponding to varying data states on the first body region.
Data Source
AI summary
A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.