Dual-Gated Oxide-Semiconductor Transistor for Stable Non-Volatile Routing
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Solution Overview
Problem
Conventional SRAM/MUX-based interconnect designs in FPGAs face challenges such as high area and power consumption, and significant time delays, while existing non-volatile switches like RRAM suffer from noise and stability issues due to 2-terminal operation.
Innovation Solution
A 4-terminal transistor with a dual-gated structure, featuring a sandwich-layer oxide-semiconductor channel with a middle layer having a lower bond dissociation energy, which eliminates the need for an additional access transistor and enhances stability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional SRAM/MUX-based interconnect design is used, then routing functionality is achieved, but area consumption increases to 70% of total chip area
Solution Approach 1:
The patent changes the operational state parameter of interconnects from volatile (SRAM/MUX) to non-volatile (FeFET), enabling reconfigurable computing without requiring large routing resources. The FeFET's ability to maintain configuration state without power allows dramatic reduction in routing area while preserving adaptability.
Solution Approach 2:
The patent transitions from 2-terminal RRAM operation to 3-terminal FeFET operation, adding a gate terminal that provides control over the conductive state. This dimensional change enables independent control of memory state and signal routing, eliminating the need for additional access transistors and reducing routing area.
2Use of energy by stationary object
If conventional SRAM/MUX-based interconnect design is used, then routing functionality is achieved, but power consumption increases to 60% of total power
Solution Approach 1:
The patent changes the power state parameter from continuous power requirement (volatile SRAM/MUX) to power-free state retention (non-volatile FeFET). The FeFET maintains its configuration without power, enabling routing functionality with dramatically reduced power consumption while improving routing efficiency through faster switching.
3Area of stationary object
If 2-terminal RRAM is used as programmable interconnect, then area efficiency is improved, but noise from interconnect signal reduces stability and reliability
Solution Approach 1:
The patent segments the RRAM functionality into two separate terminals: one for memory state control and one for signal routing. The FeFET's gate terminal handles memory programming while the source-drain terminal handles signal transmission, eliminating noise interference and improving signal stability while maintaining area efficiency.
Solution Approach 2:
The patent introduces the gate dielectric layer as an intermediary between the gate electrode and the channel. This intermediary isolates the memory storage element from the routed signal current, preventing noise from the interconnect signal from affecting the memory state while maintaining the area efficiency of non-volatile operation.
4Area of stationary object
If 3-terminal single-gated FeFET is used, then routing area is reduced, but device structure challenges and interface defects cause memory-read-write disturbance
Solution Approach 1:
The patent segments the FeFET structure into dual gates with distinct functions: one gate for memory programming and one gate for signal control. This segmentation allows independent optimization of memory operation and signal routing, eliminating the memory-read-write disturbance problem while maintaining compact routing area.
Solution Approach 2:
The patent applies different characteristics to different parts of the FeFET structure through the dual-gate design. Each gate can be independently controlled with different voltages and timing, allowing local optimization of memory write operations and read operations to prevent disturbance while maintaining overall device compactness.
Data Source
AI summary
Various embodiments may relate to a transistor including a channel, a source and a drain in contact with opposite ends of the channel. The transistor may also include a first gate, and a first gate dielectric layer including a portion between the first gate and the channel. The transistor may also include a second gate, and a second gate dielectric layer including a portion between the second gate and the channel. The channel may include a first oxide-semiconductor layer including a first oxide-semiconductor material, a second oxide-semiconductor layer including a second oxide-semiconductor material, and a middle oxide-semiconductor layer between the first oxide-semiconductor layer and the second oxide-semiconductor layer, the middle oxide-semiconductor layer including a third oxide-semiconductor material. The third oxide-semiconductor material may have a bond dissociation energy lower than a bond dissociation energy of the first oxide-semiconductor material and a bond dissociation energy of the second oxide-semiconductor material.