Dual-Ground Semiconductor ESD Protection Structure
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Solution Overview
Problem
Conventional ESD protection devices are not suitable for high voltage CMOS processes due to non-uniform current flow and shared ground issues, which affect the electrical characteristics of internal circuits, especially analog integrated circuits.
Innovation Solution
A semiconductor structure with two independent grounds and a deep N-well or N+ buried layer to isolate high voltage ESD protection circuits from low voltage internal circuits, allowing separate connections for 'dirty' and 'clean' circuits, enhancing electrical characteristics and preventing parasitic signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ESD protection device is used in high voltage CMOS process, then the internal circuit can be protected from electrostatic discharge, but the electrical characteristics of the internal circuit are affected due to shared ground and non-uniform current flow
Solution Approach 1:
The patent divides the ground system into two separate grounds: a first ground for the ESD protection device and a second ground for the internal circuit. This segmentation prevents the ESD device from affecting the electrical characteristics of the internal circuit by eliminating the shared ground problem, while still maintaining ESD protection capability.
Solution Approach 2:
The patent introduces an N+ buried layer as an intermediary structure between the ESD protection device and the internal circuit. This N+ buried layer acts as a isolation barrier that prevents parasitic signals from the ESD device from interfering with the internal circuit, while allowing both structures to coexist in the same substrate.
2Device complexity
If the ground of the ESD device shares with the low voltage internal circuit, then the structure is simplified, but the electrical characteristics of the internal circuit are affected due to ground not being fixed at zero volts
Solution Approach 1:
The patent segments the ground system into two independent grounds connected to different potential references. The first ground is connected to a first potential (e.g., ground) while the second ground is connected to a second potential (e.g., Vcc). This segmentation maintains structural simplicity while eliminating the electrical interference problem by providing separate reference potentials for each circuit.
3Reliability
If the ESD protection device is disposed between the pad and internal circuit, then the internal circuit is protected from electrostatic discharge, but the chip die area is increased
Solution Approach 1:
The patent embeds the ESD protection device structure within the existing circuit layout by using an N+ buried layer that extends beneath both the ESD device and the internal circuit. This nesting approach allows the ESD protection functionality to be integrated into the existing chip structure without requiring additional surface area, as the protection mechanism operates at a deeper level within the substrate.
Data Source
AI summary
A semiconductor structure for protecting an internal integrated circuit comprises a substrate; a plurality of first doping regions formed in the substrate and disposed substantially within an N-well; a plurality of second doping regions, formed in the substrate and disposed within an P-well; a N+ section, formed in the substrate and enclosing the N-well and the P-well; a pad, formed above the substrate and electrically connected to at least one of the first doping regions; and a first ground and a second ground respectively disposed to positions corresponding to outside and inside of the N+ section. Also, the second doping regions are isolated from the first doping regions. The first and second doping regions located within the N+ section are isolated from the substrate by the N+ section. Furthermore, the second ground is electrically connected to at least one of the second doping regions.