Dual Guard Ring Silicon Bridge Layout for In-Line Leakage Testing
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in detecting cross-layer leakage in Embedded Multi-Die Interconnection Bridge (EMIB) silicon, which is difficult to detect using standard defect metrology and often only identified at post-assembly tests, leading to delayed detection and yield reduction.
Innovation Solution
The implementation of dual guard ring designs that enable in-line testing of silicon bridges by routing test signals and ground planes through a staggered guard ring structure, allowing for early detection of defects and improving yield by monitoring wafer quality before assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard defect metrology is used for detecting cross-layer leakage in EMIB silicon, then the detection process is simple and familiar, but the detection capability is insufficient and defects are only identified at post-assembly tests
Solution Approach 1:
The testing structure is segmented into multiple functional components: guard rings for isolation, test pads for signal access, and interconnect structures for routing. This segmentation allows each component to perform its specific function efficiently while collectively enabling comprehensive cross-layer leakage detection that overcomes the limitations of standard defect metrology.
Solution Approach 2:
The patent introduces intermediary test structures (test pads and interconnects) that mediate between the conductive routing and external testing equipment. These intermediaries enable indirect detection of cross-layer leakage defects that cannot be directly observed by standard metrology tools, allowing early detection during fabrication rather than at post-assembly stage.
2Productivity
If in-line testing structures are added to enable early defect detection, then yield improves through early detection, but device complexity and fabrication steps increase
Solution Approach 1:
The patent merges testing functions with existing fabrication processes by integrating guard rings and test pads into the same fabrication steps used for creating conductive routing and interconnect structures. This merging allows in-line testing capability to be added without requiring separate dedicated fabrication steps, thereby improving yield while minimizing the increase in device complexity.
Solution Approach 2:
The guard ring structures serve multiple functions: they provide electrical isolation for test pads, enable cross-layer leakage detection, and can potentially serve as part of the final device structure. This multi-functionality reduces the need for additional dedicated test structures, balancing the improvement in manufacturing yield against the increase in device complexity.
3Ease of operation
If test pads are routed through guard rings, then in-line testing becomes possible, but the guard ring structure becomes more complex with staggered configurations
Solution Approach 1:
The patent resolves the routing conflict by transitioning to another dimension - using vertical vias to pass through guard rings rather than horizontal routing within the same layer. Test pads are positioned in staggered configurations at different locations, and metal lines route through multiple layers and vias to connect test pads to conductive routing, enabling testing accessibility without compromising guard ring isolation function.
Data Source
AI summary
Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.