Dual Half-Cycle RF Amplifier With Harmonic-Assisted Linearity
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Solution Overview
Problem
Conventional RF power amplifiers in portable wireless communication systems face challenges in achieving high power efficiency and linearity due to the use of GaAs technology, which results in reduced battery life and increased chip area consumption by baluns, necessitating a more efficient design that can support multiple communication standards and frequencies.
Innovation Solution
The proposed amplifier circuit employs a dual-unit architecture where one unit conducts during one half cycle of the input signal and the other unit during the other half cycle, with each unit comprising a main and assistant circuit unit to suppress even-order harmonics, reducing direct power consumption and using push-pull architectures with matching circuits for impedance matching and phase tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If GaAs technology is used for RF power amplifier, then power efficiency is improved, but manufacturing cost increases and integration capability decreases
Solution Approach 1:
The patent changes the material parameter from GaAs to CMOS technology, achieving a trade-off between power efficiency and manufacturing integration. The CMOS technology provides lower manufacturing costs and better integration capability while maintaining acceptable power efficiency through optimized circuit design.
Solution Approach 2:
The patent adopts CMOS technology which is cheaper and more readily available compared to GaAs technology, sacrificing some peak power efficiency for the benefit of lower cost and easier integration into standard semiconductor manufacturing processes.
2Manufacturing precision
If RF power amplifier operates in linear region, then linearity is improved, but power efficiency decreases
Solution Approach 1:
The patent divides the amplification function into multiple stages with different operating regions. The first amplifying unit operates in a nonlinear region for high efficiency while the second amplifying unit operates in a linear region to restore signal linearity, thus achieving both high power efficiency and good linearity.
Solution Approach 2:
The patent introduces an intermediate signal processing stage between the nonlinear amplification stage and the output. The intermediate stage includes filtering and linearization circuits that correct the nonlinear distortion introduced by the first amplifying unit, acting as a mediator to achieve both efficiency and linearity.
3Device complexity
If conventional single-unit amplifier architecture is used, then device complexity is reduced, but linearity and power efficiency cannot be simultaneously optimized
Solution Approach 1:
The patent segments the amplifier into multiple functional units with distinct roles: a first amplifying unit for power amplification, a filtering unit for harmonic suppression, and a second amplifying unit for linear restoration. This segmentation enables each unit to be optimized for its specific function.
Solution Approach 2:
The patent combines multiple amplifying units with different characteristics into a single integrated system. The first amplifying unit provides high efficiency operation while the second amplifying unit provides linear operation, and their combined output achieves both high power efficiency and good linearity that neither unit could achieve alone.
Data Source
AI summary
An amplifier circuit includes a first unit and a second unit. The first unit has a first amplifying unit, wherein the first amplifying unit provides a first main circuit unit and a first assistant circuit unit, and the first assistant circuit unit is configured for assisting the linearity of the first main circuit unit. The second unit includes a second amplifying unit, wherein the second amplifying unit has a second main circuit unit and a second assistant circuit unit, and the second assistant circuit unit is configured for assisting the linearity of the second main circuit unit. The first amplifying unit is configured for conducting in one half cycle of an input signal, and the second amplifying unit is configured for conducting in the other half cycle of the input signal.