Dual Hard Mask Etching for Wiring Trench Depth Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is forming a wiring trench with a design depth and completely removing the barrier film at the via hole when using a low-dielectric film as the interlayer insulating film, due to increased etching rates and high etching selection ratios, which can result in excessive digging or open defects.
Innovation Solution
A method using a two-layer structure hard mask in the dual damascene process, where the first hard mask is etched using the second hard mask as a mask, and the barrier film at the via hole bottom is partially removed, allowing for precise etching of the wiring trench and barrier film removal, employing specific etching gases like C4F6/N2 and CHF3 to control etching rates and selection ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low-dielectric film is used as the interlayer insulating film, then the speed of the semiconductor device is increased, but the etching rate increases and the etching selection ratio becomes high, making it difficult to form a wiring trench with design depth and completely remove the barrier film
Solution Approach 1:
The patent applies segmentation by dividing the mask structure into two distinct layers: a first mask layer and a second mask layer with different etching properties. This allows separate control of via hole formation and wiring trench formation processes, enabling precise depth control of the wiring trench while ensuring complete barrier film removal at via holes, thus resolving the contradiction between device speed improvement and manufacturing precision.
2Ease of manufacture
If a single mask is used for both via hole formation and wiring trench formation, then the process is simpler, but it is difficult to achieve both design depth precision and complete barrier film removal simultaneously
Solution Approach 1:
The patent segments the mask into two functional layers with different etching characteristics. The first mask layer has high etching selectivity for the low-dielectric film, enabling precise wiring trench depth control. The second mask layer has different etching properties that allow complete barrier film removal at via holes. This segmentation resolves the contradiction by maintaining process simplicity while achieving precise depth control through the coordinated action of two specialized mask layers.
3Productivity
If the etching rate is increased to improve productivity, then the manufacturing efficiency is improved, but the wiring trench depth becomes difficult to control and excessive digging occurs
Solution Approach 1:
The patent applies local quality by creating mask layers with spatially varying etching properties. The first mask layer is designed with high etching selectivity specifically for the low-dielectric film region, allowing fast etching where needed while maintaining precision control. The second mask layer provides different local etching characteristics for via hole regions. This local differentiation enables high productivity through increased etching rates while preventing excessive digging through selective etching control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a wiring trench with a design depth and complete removal of the barrier film, preventing excessive digging and open defects, while maintaining high etching rates and selection ratios, even with low-dielectric films.
Implementation Method 1
removing the insulating film, the first mask, and the second mask to form a via hole in the insulating film
Implementation Method 2
removing the second mask in a wiring trench forming region including the via hole
Implementation Method 3
etching the first mask using the second mask as a mask to remove the first mask in the wiring trench forming region
Implementation Method 4
etching the barrier film at the bottom of the via hole to partially remove the barrier film at the bottom of the via hole
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming in order a barrier film, an insulating film, a first mask, and a second mask having etching properties different from those of the first mask on a substrate, removing the insulating film, the first mask, and the second mask to form a via hole in the insulating film, removing the second mask in a wiring trench forming region including the via hole, and etching the first mask using the second mask as a mask to remove the first mask in the wiring trench forming region. Removing the first mask in the wiring trench forming region includes etching the first mask and etching the barrier film at the bottom of the via hole to partially remove the barrier film at the bottom of the via hole.