Dual Hard Mask Gate Structure Preventing Contact Shorts
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Solution Overview
Problem
The fabrication of semiconductor devices faces challenges with contact-to-gate shorts due to misalignment of contact plugs, which become exacerbated as transistor gate pitch dimensions are scaled down, leading to electrical contact with the gate electrode and short circuits.
Innovation Solution
The implementation of dual hard mask layers, where a first hard mask is deposited and recessed, followed by a second hard mask layer that covers any voids in the first layer, forming a protective cap over the gate electrode to prevent shorts during contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed to connect to source and drain regions, then electrical connections are established, but misalignment may cause contact-to-gate shorts especially as gate pitch dimensions are scaled down
Solution Approach 1:
A hard mask layer is deposited over the gate electrode before contact formation to create a protective barrier. This preliminary protective action prevents contact material from reaching the gate electrode even if misalignment occurs during contact plug formation, thereby eliminating contact-to-gate shorts while maintaining reliable electrical connections to source and drain regions
Solution Approach 2:
The hard mask layer serves as an intermediary protective layer between the contact plugs and the gate electrode. This intermediate barrier physically separates the contact material from the gate electrode, preventing direct electrical contact and shorts while allowing the contact plugs to maintain their electrical connection function to the source and drain regions
2Productivity
If gate pitch dimensions are scaled down to increase device density, then more transistors can be integrated, but the risk of contact-to-gate shorts increases due to reduced alignment margin
Solution Approach 1:
The hard mask layer is deposited in advance over the gate electrode structure before contact formation begins. This preliminary protective measure compensates for reduced alignment margins by providing a physical barrier that prevents contact material from reaching the gate electrode, enabling safe scaling to smaller gate pitch dimensions without increasing short circuit risk
Solution Approach 2:
The hard mask layer acts as an intermediary protective structure that decouples the alignment precision requirement from the physical risk of shorts. By introducing this intermediate barrier, the system can tolerate larger alignment variations that would otherwise be unacceptable at scaled dimensions, thereby enabling higher device integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual hard mask layers effectively prevent electrical shorts to the gate electrode even when contact misalignment occurs, ensuring reliable contact formation without short circuits, especially in scaled-down transistor gate pitches.
Implementation Method 1
depositing a first hard mask layer on a recessed gate stack arranged between gate spacers
Implementation Method 2
depositing a first hard mask layer on a recessed gate stack arranged between gate spacers
Data Source
AI summary
A method of fabricating a semiconductor device includes depositing a first hard mask layer on a recessed gate stack arranged between gate spacers. The method further includes depositing a second hard mask layer on the first hard mask layer between the gate spacers.