Dual Hard Mask Gate Fabrication for LV/MV Leakage Control
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in integrating high-voltage and FinFET devices, particularly in controlling current leakage and breakdown voltage as device scaling decreases, leading to performance issues.
Innovation Solution
A method is developed to fabricate semiconductor devices by forming substrates with distinct low-voltage and medium-voltage regions, creating different thicknesses of hard masks on gate structures using a series of etching and deposition processes, including the formation of metal gates and hard masks with varying thicknesses to address the specific voltage requirements of each region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single hard mask thickness is used for both low-voltage and medium-voltage regions, then the fabrication process is simpler, but the breakdown voltage control and current leakage prevention are compromised
Solution Approach 1:
The patent applies different hard mask thicknesses to different voltage regions (LV and MV) based on their specific electrical requirements. The LV region receives a first hard mask thickness while the MV region receives a second hard mask thickness, allowing each region to have optimized local properties for its voltage operation characteristics.
Solution Approach 2:
The substrate is divided into distinct low-voltage and medium-voltage regions, each receiving tailored hard mask processing. The fabrication process is segmented into separate etching and deposition sequences that selectively form different hard mask thicknesses on different regions, enabling region-specific optimization.
2Productivity
If device scaling is continued to decrease size, then integration density is improved, but current leakage and breakdown voltage control become more difficult
Solution Approach 1:
Different hard mask thicknesses are applied to LV and MV regions to locally optimize electrical characteristics. This local differentiation allows compact integration while maintaining proper voltage control and minimizing leakage currents in each region according to its specific requirements.
3Reliability
If FinFET technology is used to increase channel control, then device performance is improved, but the complexity of fabricating different gate structures increases
Solution Approach 1:
The fabrication process is divided into separate sequences for forming metal gates and hard masks on LV versus MV regions. This segmentation allows independent optimization of each region's gate structure while following a systematic, repeatable process framework that manages complexity.
Solution Approach 2:
Patterned masks are formed on metal gates before hard mask deposition, and selective etching is performed to prepare surfaces in advance. These preliminary actions ensure that subsequent hard mask formation occurs on properly prepared regions, simplifying the overall multi-step fabrication process.
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.