Dual Hard Mask Planarization for 3D Memory Contact Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional semiconductor structures face issues with irregularities in layers due to defects, leading to potential failures in memory devices, necessitating a method to prevent such failures by ensuring precise formation of conductive and insulating layers.
Innovation Solution
A method involving the use of two hard mask layers, where a first hard mask layer is used as a sacrificial layer to planarize the structure, and a second hard mask layer is formed to ensure accurate formation of contacts through the dielectric layers, addressing irregularities and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single hard mask layer is used in the conventional process, then the process complexity is low, but the manufacturing precision deteriorates due to irregular portions in layers causing short circuits
Solution Approach 1:
The single hard mask layer is segmented into two separate hard mask layers: a first hard mask layer used as a sacrificial layer for planarization, and a second hard mask layer used as the actual masking layer for contact hole formation. This segmentation allows each layer to perform its specific function optimally, preventing short circuits while maintaining process control.
Solution Approach 2:
The first hard mask layer acts as an intermediary sacrificial layer that is temporarily introduced to achieve planarization of the stacked structure. After serving its purpose as a planarization template, it is selectively removed, allowing the second hard mask layer to provide the necessary masking precision for contact formation without interference from underlying irregularities.
2Shape
If the planarization process continues through the hard mask layer, then the surface flatness is improved, but the hard mask layer is damaged and manufacturing precision deteriorates
Solution Approach 1:
The first hard mask layer is formed in advance as a sacrificial planarization layer. The planarization process (CMP) is deliberately stopped at this first hard mask layer to achieve the desired surface flatness without penetrating through to damage the second hard mask layer or underlying structures. This preliminary action protects the critical second hard mask layer while still providing the necessary planarization.
Solution Approach 2:
The planarization function is extracted and performed by the first hard mask layer as a sacrificial element. After the planarization process stops at the first hard mask layer, this sacrificial layer is selectively removed in a subsequent step, allowing the second hard mask layer to remain intact and undamaged for precise contact hole patterning.
3Reliability
If irregular portions in stacked layers are not addressed, then the process simplicity is maintained, but the reliability deteriorates due to short circuits between conductive layers
Solution Approach 1:
The masking function is segmented into two separate hard mask layers, each serving a distinct purpose. The first hard mask layer addresses planarization needs and is removed after serving its function, while the second hard mask layer provides the necessary precision masking for contact formation. This segmentation prevents short circuits by ensuring proper isolation between conductive layers.
Solution Approach 2:
The first hard mask layer serves as an intermediary sacrificial structure that enables proper planarization of the stacked memory structure. By providing a removable planarization template, it ensures that subsequent layers can be formed with proper alignment and spacing, preventing short circuits between conductive layers while maintaining overall device reliability.
Data Source
AI summary
A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.