Dual Hash Cache Line Determination for Switch Memory Efficiency
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Solution Overview
Problem
In network switches, determining network ports for packet forwarding is inefficient due to large address ranges requiring significant memory and the trade-off between cache size and hashing function-induced aliasing in N-way set associative caches.
Innovation Solution
A method using a main hash table in external memory and an auxiliary hash table in internal memory, where a key associated with a destination address generates both hashes to determine a bucket and an entry, allowing efficient lookup and reducing memory access by using a pseudo code for packet forwarding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a hash function is used to calculate cache index, then memory usage is reduced, but aliasing problems are introduced
Solution Approach 1:
The cache is divided into N-way set associative structure, where each hash index points to a set of N cache lines instead of a single line. This segmentation allows the system to maintain reduced memory usage through hashing while resolving aliasing by providing multiple candidate lines to choose from, thereby improving reliability.
Solution Approach 2:
The patent introduces an additional dimension by using both the hash index and the set associate number to uniquely identify cache lines. Instead of a single-dimensional hash-to-line mapping, the system creates a two-dimensional mapping (hash index, set associate number) that reduces collisions while maintaining memory efficiency.
2Reliability
If cache size is increased to reduce aliasing, then reliability improves, but memory resources are consumed
Solution Approach 1:
The system dynamically selects from N cache lines within each set based on the specific access pattern and replacement policies (such as LRU - Least Recently Used). This dynamic selection allows the cache to adapt to different workloads without requiring a fixed large size, maintaining reliability while optimizing memory resource usage.
Solution Approach 2:
The patent allows the parameter N (number of ways in set associative cache) to be configured based on specific application requirements. By changing this parameter, the system can adjust the balance between reliability (reducing aliasing) and memory resource consumption according to different operational contexts.
3Quantity of substance
If forwarding table is implemented as hash table, then memory resources are reduced, but lookup efficiency decreases due to collisions
Solution Approach 1:
The hash table is segmented into multiple buckets, where each bucket contains multiple cache lines. This segmentation reduces the probability of collisions affecting lookup efficiency because collisions are distributed across multiple lines within each bucket rather than causing direct conflicts. The lookup process remains efficient while memory resources are conserved.
Solution Approach 2:
The set associative structure acts as an intermediary between the hash index and the actual data storage. Instead of direct hash-to-data mapping, the hash index first maps to a set of candidate lines, and then the correct line is identified. This intermediary layer reduces the impact of collisions on lookup efficiency while maintaining compact memory usage.
Data Source
AI summary
A method and apparatus for determining a cache line in an N-way set associative cache are disclosed. In one example embodiment, a key associated with a cache line is obtained. A main hash is generated using a main hash function on the key. An auxiliary hash is generated using an auxiliary hash function on the key. A bucket in a main hash table residing in an external memory is determined using the main hash. An entry in a bucket in an auxiliary hash table residing in an internal memory is determined using the determined bucket and the auxiliary hash. The cache line in the main hash table is determined using the determined entry in the auxiliary hash table.